rogue v6.3.0: scripts/updatePcieFpga.py failing

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    • Type: Bug
    • Resolution: resolved
    • Priority: Blocker
    • Component/s: None
    • None

      Update: Determined that the issue is created in this rogue pull request:
      https://github.com/slaclab/rogue/pull/1007

      I have isolated the isolation issue being a change made to one or more of these files:

      • src/rogue/interfaces/memory/Block.cpp
      • src/rogue/interfaces/memory/Variable.cpp
      • include/rogue/interfaces/memory/Variable.h

      -----------------------------------------------------------------------------------------------------------------------------

      v6.3.0 = broken

      V6.2.0 = works

      Static aes-stream-driver version (6.2.1)

      (rogue_v6.3.0) ruckman@rdsrv403:~/projects/pgp-pcie-apps/software$ python scripts/updatePcieFpga.py --path ../firmware/targets/XilinxVariumC1100/XilinxVariumC1100DmaLoopback/images/
      Rogue/pyrogue version v6.3.0. https://github.com/slaclab/rogue
      Basedir = /afs/slac.stanford.edu/u/re/ruckman/projects/pgp-pcie-apps/firmware/submodules/axi-pcie-core/scripts
      WARNING: PcieTop.AxiPcieCore.numDmaLanes = 1 != PcieTop.AxiPcieCore.AxiVersion.DMA_SIZE_G = 4
      #########################################
      Current Firmware Loaded on the PCIe card:
      #########################################
      Path         = PcieTop.AxiPcieCore.AxiVersion
      FwVersion    = 0x3080000
      UpTime       = 3 days, 20:51:58
      GitHash      = 0x9316db7dd5a6a61af8c9d1ba392f0579a194c738
      XilinxDnaId  = 0x40020000015060482cf06445
      FwTarget     = Lcls2XilinxC1100Pgp4_6Gbps
      BuildEnv     = Vivado v2023.1
      BuildServer  = rdsrv404 (Ubuntu 20.04.6 LTS)
      BuildDate    = Mon 05 Feb 2024 09:37:35 PM PST
      Builder      = ruckman
      #########################################
      0 : ../firmware/targets/XilinxVariumC1100/XilinxVariumC1100DmaLoopback/images/XilinxVariumC1100DmaLoopback-0x02050000-20240706114440-ruckman-71fd058
      1 : Exit
      Enter image to program into the PCIe card's PROM: 0
      Selected image does not match current image Lcls2XilinxC1100Pgp4_6Gbps.
      Are you sure? (y/n): y
      PcieTop.AxiPcieCore.AxiMicronN25Q[0].LoadMcsFile: ../firmware/targets/XilinxVariumC1100/XilinxVariumC1100DmaLoopback/images/XilinxVariumC1100DmaLoopback-0x02050000-20240706114440-ruckman-71fd058.mcs
      PROM Manufacturer ID Code  = 0x20
      PROM Manufacturer Type     = 0xbb
      PROM Manufacturer Capacity = 0x21
      PROM Status Register       = 0x2
      PROM Volatile Config Reg   = 0xfb
      Reading .MCS:    [####################################]  100%
      Erasing PROM:    [####################################]  100%
      Writing PROM:    [####################################]  100%
      Verifying PROM:  [------------------------------------]    0%
      Addr = 0x1002004: MCS = 0xff != PROM = 0x20
      
      ERROR:pyrogue.Command.BaseCommand.PcieTop.AxiPcieCore.AxiMicronN25Q[0].LoadMcsFile:verifyProm() Failed
      
      Traceback (most recent call last):
        File "/afs/slac.stanford.edu/g/reseng/vol31/anaconda/anaconda3/envs/rogue_v6.3.0/lib/python3.9/site-packages/pyrogue/_Command.py", line 119, in _doFunc
          ret = self._functionWrap(function=self._function, root=self.root, dev=self.parent, cmd=self, arg=arg)
        File "<string>", line 1, in <lambda>
        File "/afs/slac.stanford.edu/u/re/ruckman/projects/pgp-pcie-apps/firmware/submodules/axi-pcie-core/scripts/../../surf/python/surf/devices/micron/_AxiMicronN25Q.py", line 200, in _LoadMcsFile
          self.verifyProm()
        File "/afs/slac.stanford.edu/u/re/ruckman/projects/pgp-pcie-apps/firmware/submodules/axi-pcie-core/scripts/../../surf/python/surf/devices/micron/_AxiMicronN25Q.py", line 328, in verifyProm
          raise surf.misc.McsException('verifyProm() Failed\n\n')
      surf.misc._McsReader.McsException: verifyProm() Failed
      
      
      Traceback (most recent call last):
        File "/afs/slac.stanford.edu/u/re/ruckman/projects/pgp-pcie-apps/software/scripts/updatePcieFpga.py", line 186, in <module>
          PROM_PRI.LoadMcsFile(pri)
        File "/afs/slac.stanford.edu/g/reseng/vol31/anaconda/anaconda3/envs/rogue_v6.3.0/lib/python3.9/site-packages/pyrogue/_Command.py", line 93, in __call__
          return self._doFunc(arg)
        File "/afs/slac.stanford.edu/g/reseng/vol31/anaconda/anaconda3/envs/rogue_v6.3.0/lib/python3.9/site-packages/pyrogue/_Command.py", line 130, in _doFunc
          raise e
        File "/afs/slac.stanford.edu/g/reseng/vol31/anaconda/anaconda3/envs/rogue_v6.3.0/lib/python3.9/site-packages/pyrogue/_Command.py", line 119, in _doFunc
          ret = self._functionWrap(function=self._function, root=self.root, dev=self.parent, cmd=self, arg=arg)
        File "<string>", line 1, in <lambda>
        File "/afs/slac.stanford.edu/u/re/ruckman/projects/pgp-pcie-apps/firmware/submodules/axi-pcie-core/scripts/../../surf/python/surf/devices/micron/_AxiMicronN25Q.py", line 200, in _LoadMcsFile
          self.verifyProm()
        File "/afs/slac.stanford.edu/u/re/ruckman/projects/pgp-pcie-apps/firmware/submodules/axi-pcie-core/scripts/../../surf/python/surf/devices/micron/_AxiMicronN25Q.py", line 328, in verifyProm
          raise surf.misc.McsException('verifyProm() Failed\n\n')
      surf.misc._McsReader.McsException: verifyProm() Failed
       

              Assignee:
              Ryan Herbst
              Reporter:
              Larry Ruckman
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              Watchers:
              3 Start watching this issue

                Created:
                Updated:
                Resolved: