Rogue/pyrogue version v6.3.0. https://github.com/slaclab/rogue 1721179794.679616:pyrogue.memory.Master: Starting logger with level = 10 1721179794.679618:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.681399:pyrogue.axi.AxiMemMap: Starting logger with level = 10 1721179794.681457:pyrogue.memory.Master: Starting logger with level = 10 1721179794.681457:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.681481:pyrogue.axi.AxiMemMap: PID=3034, TID=3059 1721179794.681642:pyrogue.memory.Master: Starting logger with level = 10 1721179794.681643:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.683782:pyrogue.memory.Master: Starting logger with level = 10 1721179794.683784:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.684276:pyrogue.memory.Master: Starting logger with level = 10 1721179794.684277:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.685051:pyrogue.memory.Master: Starting logger with level = 10 1721179794.685052:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.685819:pyrogue.memory.Master: Starting logger with level = 10 1721179794.685820:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.686478:pyrogue.memory.Master: Starting logger with level = 10 1721179794.686479:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.687781:pyrogue.memory.Master: Starting logger with level = 10 1721179794.687782:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.688245:pyrogue.memory.Master: Starting logger with level = 10 1721179794.688246:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.688726:pyrogue.memory.Master: Starting logger with level = 10 1721179794.688727:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.689118:pyrogue.memory.Master: Starting logger with level = 10 1721179794.689119:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.689261:pyrogue.memory.Master: Starting logger with level = 10 1721179794.689262:pyrogue.memory.Hub: Starting logger with level = 10 1721179794.690463:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690474:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaVersion: Starting logger with level = 10 1721179794.690476:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaVersion: Adding variable FpgaVersion to block PcieTop.AxiPcieCore.AxiVersion.FpgaVersion at offset 0x00000000, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690485:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaVersion: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690495:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690498:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.ScratchPad: Starting logger with level = 10 1721179794.690500:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.ScratchPad: Adding variable ScratchPad to block PcieTop.AxiPcieCore.AxiVersion.ScratchPad at offset 0x00000004, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 1 lx 1721179794.690501:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.ScratchPad: Done adding variables. Verify Mask 000 - 003: 0xff 0xff 0xff 0xff 1721179794.690505:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690507:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UpTimeCnt: Starting logger with level = 10 1721179794.690508:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UpTimeCnt: Adding variable UpTimeCnt to block PcieTop.AxiPcieCore.AxiVersion.UpTimeCnt at offset 0x00000008, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690509:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UpTimeCnt: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690512:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690515:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReloadHalt: Starting logger with level = 10 1721179794.690515:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReloadHalt: Adding variable FpgaReloadHalt to block PcieTop.AxiPcieCore.AxiVersion.FpgaReloadHalt at offset 0x00000100, bitIdx=0, bitOffset 0, bitSize 1, mode RW, verifyEn 1 lx 1721179794.690524:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReloadHalt: Done adding variables. Verify Mask 000 - 003: 0x01 0x00 0x00 0x00 1721179794.690528:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690530:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReload: Starting logger with level = 10 1721179794.690531:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReload: Adding variable FpgaReload to block PcieTop.AxiPcieCore.AxiVersion.FpgaReload at offset 0x00000104, bitIdx=0, bitOffset 0, bitSize 1, mode WO, verifyEn 0 lx 1721179794.690531:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReload: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690535:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690537:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReloadAddress: Starting logger with level = 10 1721179794.690538:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReloadAddress: Adding variable FpgaReloadAddress to block PcieTop.AxiPcieCore.AxiVersion.FpgaReloadAddress at offset 0x00000108, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 1 lx 1721179794.690539:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReloadAddress: Done adding variables. Verify Mask 000 - 003: 0xff 0xff 0xff 0xff 1721179794.690542:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690544:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UserReset: Starting logger with level = 10 1721179794.690545:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UserReset: Adding variable UserReset to block PcieTop.AxiPcieCore.AxiVersion.UserReset at offset 0x0000010c, bitIdx=0, bitOffset 0, bitSize 1, mode RW, verifyEn 1 lx 1721179794.690546:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UserReset: Done adding variables. Verify Mask 000 - 003: 0x01 0x00 0x00 0x00 1721179794.690549:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690551:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FdSerial: Starting logger with level = 10 1721179794.690552:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FdSerial: Adding variable FdSerial to block PcieTop.AxiPcieCore.AxiVersion.FdSerial at offset 0x00000300, bitIdx=0, bitOffset 0, bitSize 64, mode RO, verifyEn 1 lx 1721179794.690553:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FdSerial: Done adding variables. Verify Mask 000 - 007: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690556:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690558:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_SIZE_G: Starting logger with level = 10 1721179794.690559:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_SIZE_G: Adding variable DMA_SIZE_G to block PcieTop.AxiPcieCore.AxiVersion.DMA_SIZE_G at offset 0x00000400, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690559:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_SIZE_G: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690562:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690565:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.Reserved: Starting logger with level = 10 1721179794.690565:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.Reserved: Adding variable Reserved to block PcieTop.AxiPcieCore.AxiVersion.Reserved at offset 0x00000404, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690566:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.Reserved: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690569:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690571:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DRIVER_TYPE_ID_G: Starting logger with level = 10 1721179794.690572:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DRIVER_TYPE_ID_G: Adding variable DRIVER_TYPE_ID_G to block PcieTop.AxiPcieCore.AxiVersion.DRIVER_TYPE_ID_G at offset 0x00000408, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690574:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DRIVER_TYPE_ID_G: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690578:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690580:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.XIL_DEVICE_G: Starting logger with level = 10 1721179794.690580:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.XIL_DEVICE_G: Adding variable XIL_DEVICE_G to block PcieTop.AxiPcieCore.AxiVersion.XIL_DEVICE_G at offset 0x0000040c, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690581:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.XIL_DEVICE_G: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690584:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690586:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_CLK_FREQ_C: Starting logger with level = 10 1721179794.690587:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_CLK_FREQ_C: Adding variable DMA_CLK_FREQ_C to block PcieTop.AxiPcieCore.AxiVersion.DMA_CLK_FREQ_C at offset 0x00000410, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690587:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_CLK_FREQ_C: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690590:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690593:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BOOT_PROM_G: Starting logger with level = 10 1721179794.690593:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BOOT_PROM_G: Adding variable BOOT_PROM_G to block PcieTop.AxiPcieCore.AxiVersion.BOOT_PROM_G at offset 0x00000414, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690594:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BOOT_PROM_G: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690597:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690600:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Starting logger with level = 10 1721179794.690601:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Adding variable DMA_AXIS_CONFIG_G_TDATA_BYTES_C to block PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C at offset 0x00000418, bitIdx=0, bitOffset 24, bitSize 8, mode RO, verifyEn 1 lx 1721179794.690601:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Adding variable DMA_AXIS_CONFIG_G_TDEST_BITS_C to block PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C at offset 0x00000418, bitIdx=0, bitOffset 20, bitSize 4, mode RO, verifyEn 1 lx 1721179794.690602:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Adding variable DMA_AXIS_CONFIG_G_TUSER_BITS_C to block PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C at offset 0x00000418, bitIdx=0, bitOffset 16, bitSize 4, mode RO, verifyEn 1 lx 1721179794.690602:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Adding variable DMA_AXIS_CONFIG_G_TID_BITS_C to block PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C at offset 0x00000418, bitIdx=0, bitOffset 12, bitSize 4, mode RO, verifyEn 1 lx 1721179794.690603:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Adding variable DMA_AXIS_CONFIG_G_TKEEP_MODE_C to block PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C at offset 0x00000418, bitIdx=0, bitOffset 8, bitSize 4, mode RO, verifyEn 1 lx 1721179794.690603:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Adding variable DMA_AXIS_CONFIG_G_TUSER_MODE_C to block PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C at offset 0x00000418, bitIdx=0, bitOffset 4, bitSize 4, mode RO, verifyEn 1 lx 1721179794.690603:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Adding variable DMA_AXIS_CONFIG_G_TSTRB_EN_C to block PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C at offset 0x00000418, bitIdx=0, bitOffset 1, bitSize 1, mode RO, verifyEn 1 lx 1721179794.690606:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Adding variable AppReset to block PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C at offset 0x00000418, bitIdx=0, bitOffset 0, bitSize 1, mode RO, verifyEn 1 lx 1721179794.690607:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690610:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690613:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C: Starting logger with level = 10 1721179794.690613:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C: Adding variable AXI_PCIE_CONFIG_C_ADDR_WIDTH_C to block PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C at offset 0x0000041c, bitIdx=0, bitOffset 24, bitSize 8, mode RO, verifyEn 1 lx 1721179794.690614:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C: Adding variable AXI_PCIE_CONFIG_C_DATA_BYTES_C to block PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C at offset 0x0000041c, bitIdx=0, bitOffset 16, bitSize 8, mode RO, verifyEn 1 lx 1721179794.690614:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C: Adding variable AXI_PCIE_CONFIG_C_ID_BITS_C to block PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C at offset 0x0000041c, bitIdx=0, bitOffset 8, bitSize 8, mode RO, verifyEn 1 lx 1721179794.690614:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C: Adding variable AXI_PCIE_CONFIG_C_LEN_BITS_C to block PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C at offset 0x0000041c, bitIdx=0, bitOffset 0, bitSize 8, mode RO, verifyEn 1 lx 1721179794.690615:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690618:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690620:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AppClkFreq: Starting logger with level = 10 1721179794.690621:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AppClkFreq: Adding variable AppClkFreq to block PcieTop.AxiPcieCore.AxiVersion.AppClkFreq at offset 0x00000420, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690622:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AppClkFreq: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690625:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690627:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.PCIE_HW_TYPE_G: Starting logger with level = 10 1721179794.690628:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.PCIE_HW_TYPE_G: Adding variable PCIE_HW_TYPE_G to block PcieTop.AxiPcieCore.AxiVersion.PCIE_HW_TYPE_G at offset 0x00000424, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690628:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.PCIE_HW_TYPE_G: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690631:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690634:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceId: Starting logger with level = 10 1721179794.690634:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceId: Adding variable DeviceId to block PcieTop.AxiPcieCore.AxiVersion.DeviceId at offset 0x00000500, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690635:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceId: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690638:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690640:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.GitHash: Starting logger with level = 10 1721179794.690642:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.GitHash: Adding variable GitHash to block PcieTop.AxiPcieCore.AxiVersion.GitHash at offset 0x00000600, bitIdx=0, bitOffset 0, bitSize 160, mode RO, verifyEn 1 lx 1721179794.690643:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.GitHash: Done adding variables. Verify Mask 000 - 009: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690644:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.GitHash: Done adding variables. Verify Mask 010 - 019: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690647:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690649:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceDna: Starting logger with level = 10 1721179794.690650:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceDna: Adding variable DeviceDna to block PcieTop.AxiPcieCore.AxiVersion.DeviceDna at offset 0x00000700, bitIdx=0, bitOffset 0, bitSize 128, mode RO, verifyEn 1 lx 1721179794.690651:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceDna: Done adding variables. Verify Mask 000 - 009: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690652:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceDna: Done adding variables. Verify Mask 010 - 015: 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690655:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690658:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Starting logger with level = 10 1721179794.690659:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Adding variable BuildStamp to block PcieTop.AxiPcieCore.AxiVersion.BuildStamp at offset 0x00000800, bitIdx=0, bitOffset 0, bitSize 2048, mode RO, verifyEn 1 lx 1721179794.690660:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 000 - 009: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690660:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 010 - 019: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690661:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 020 - 029: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690662:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 030 - 039: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690663:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 040 - 049: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690663:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 050 - 059: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690664:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 060 - 069: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690665:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 070 - 079: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690666:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 080 - 089: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690666:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 090 - 099: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690667:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 100 - 109: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690668:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 110 - 119: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690668:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 120 - 129: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690671:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 130 - 139: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690672:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 140 - 149: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690673:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 150 - 159: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690673:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 160 - 169: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690674:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 170 - 179: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690675:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 180 - 189: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690676:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 190 - 199: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690676:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 200 - 209: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690677:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 210 - 219: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690678:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 220 - 229: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690678:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 230 - 239: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690679:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 240 - 249: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690680:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Done adding variables. Verify Mask 250 - 255: 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690933:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690938:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameCnt: Starting logger with level = 10 1721179794.690939:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameCnt: Adding variable FrameCnt to block PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameCnt at offset 0x00000004, bitIdx=0, bitOffset 0, bitSize 64, mode RO, verifyEn 1 lx 1721179794.690940:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameCnt: Done adding variables. Verify Mask 000 - 007: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690947:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690950:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRate: Starting logger with level = 10 1721179794.690951:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRate: Adding variable FrameRate to block PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRate at offset 0x0000000c, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690952:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRate: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690956:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690958:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMax: Starting logger with level = 10 1721179794.690959:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMax: Adding variable FrameRateMax to block PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMax at offset 0x00000010, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690960:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMax: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690966:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690969:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMin: Starting logger with level = 10 1721179794.690969:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMin: Adding variable FrameRateMin to block PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMin at offset 0x00000014, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.690970:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMin: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.690974:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690976:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidth: Starting logger with level = 10 1721179794.690977:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidth: Adding variable RawBandwidth to block PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidth at offset 0x00000018, bitIdx=0, bitOffset 0, bitSize 64, mode RO, verifyEn 1 lx 1721179794.690978:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidth: Done adding variables. Verify Mask 000 - 007: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690981:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690984:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMax: Starting logger with level = 10 1721179794.690985:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMax: Adding variable RawBandwidthMax to block PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMax at offset 0x00000020, bitIdx=0, bitOffset 0, bitSize 64, mode RO, verifyEn 1 lx 1721179794.690986:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMax: Done adding variables. Verify Mask 000 - 007: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690989:pyrogue.memory.Master: Starting logger with level = 10 1721179794.690992:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMin: Starting logger with level = 10 1721179794.690992:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMin: Adding variable RawBandwidthMin to block PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMin at offset 0x00000028, bitIdx=0, bitOffset 0, bitSize 64, mode RO, verifyEn 1 lx 1721179794.690993:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMin: Done adding variables. Verify Mask 000 - 007: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.690997:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691000:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSize: Starting logger with level = 10 1721179794.691000:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSize: Adding variable FrameSize to block PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSize at offset 0x00000030, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.691001:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSize: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.691005:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691007:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMax: Starting logger with level = 10 1721179794.691008:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMax: Adding variable FrameSizeMax to block PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMax at offset 0x00000034, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.691008:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMax: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.691012:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691015:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMin: Starting logger with level = 10 1721179794.691017:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMin: Adding variable FrameSizeMin to block PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMin at offset 0x00000038, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.691018:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMin: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.691080:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691085:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Starting logger with level = 10 1721179794.691086:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Adding variable CntRst to block PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 0, bitSize 1, mode WO, verifyEn 0 lx 1721179794.691086:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TDATA_BYTES_C to block PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 24, bitSize 8, mode RO, verifyEn 1 lx 1721179794.691087:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TDEST_BITS_C to block PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 20, bitSize 4, mode RO, verifyEn 1 lx 1721179794.691087:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TUSER_BITS_C to block PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 16, bitSize 4, mode RO, verifyEn 1 lx 1721179794.691088:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TID_BITS_C to block PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 12, bitSize 4, mode RO, verifyEn 1 lx 1721179794.691088:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TKEEP_MODE_C to block PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 8, bitSize 4, mode RO, verifyEn 1 lx 1721179794.691088:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TUSER_MODE_C to block PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 4, bitSize 4, mode RO, verifyEn 1 lx 1721179794.691089:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TSTRB_EN_C to block PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 1, bitSize 1, mode RO, verifyEn 1 lx 1721179794.691089:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Adding variable COMMON_CLK_G to block PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 0, bitSize 1, mode RO, verifyEn 1 lx 1721179794.691090:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.691410:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691416:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameCnt: Starting logger with level = 10 1721179794.691417:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameCnt: Adding variable FrameCnt to block PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameCnt at offset 0x00000004, bitIdx=0, bitOffset 0, bitSize 64, mode RO, verifyEn 1 lx 1721179794.691419:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameCnt: Done adding variables. Verify Mask 000 - 007: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.691425:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691428:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRate: Starting logger with level = 10 1721179794.691428:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRate: Adding variable FrameRate to block PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRate at offset 0x0000000c, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.691429:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRate: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.691437:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691440:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMax: Starting logger with level = 10 1721179794.691441:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMax: Adding variable FrameRateMax to block PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMax at offset 0x00000010, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.691441:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMax: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.691446:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691448:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMin: Starting logger with level = 10 1721179794.691449:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMin: Adding variable FrameRateMin to block PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMin at offset 0x00000014, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.691449:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMin: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.691456:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691459:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidth: Starting logger with level = 10 1721179794.691459:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidth: Adding variable RawBandwidth to block PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidth at offset 0x00000018, bitIdx=0, bitOffset 0, bitSize 64, mode RO, verifyEn 1 lx 1721179794.691460:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidth: Done adding variables. Verify Mask 000 - 007: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.691464:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691467:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMax: Starting logger with level = 10 1721179794.691467:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMax: Adding variable RawBandwidthMax to block PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMax at offset 0x00000020, bitIdx=0, bitOffset 0, bitSize 64, mode RO, verifyEn 1 lx 1721179794.691468:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMax: Done adding variables. Verify Mask 000 - 007: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.691472:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691475:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMin: Starting logger with level = 10 1721179794.691475:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMin: Adding variable RawBandwidthMin to block PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMin at offset 0x00000028, bitIdx=0, bitOffset 0, bitSize 64, mode RO, verifyEn 1 lx 1721179794.691476:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMin: Done adding variables. Verify Mask 000 - 007: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.691480:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691483:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSize: Starting logger with level = 10 1721179794.691483:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSize: Adding variable FrameSize to block PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSize at offset 0x00000030, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.691484:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSize: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.691495:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691497:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMax: Starting logger with level = 10 1721179794.691501:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMax: Adding variable FrameSizeMax to block PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMax at offset 0x00000034, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.691501:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMax: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.691505:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691508:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMin: Starting logger with level = 10 1721179794.691508:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMin: Adding variable FrameSizeMin to block PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMin at offset 0x00000038, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.691509:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMin: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.691603:pyrogue.memory.Master: Starting logger with level = 10 1721179794.691611:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Starting logger with level = 10 1721179794.691612:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Adding variable CntRst to block PcieTop.AxiPcieCore.DmaObAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 0, bitSize 1, mode WO, verifyEn 0 lx 1721179794.691612:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TDATA_BYTES_C to block PcieTop.AxiPcieCore.DmaObAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 24, bitSize 8, mode RO, verifyEn 1 lx 1721179794.691613:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TDEST_BITS_C to block PcieTop.AxiPcieCore.DmaObAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 20, bitSize 4, mode RO, verifyEn 1 lx 1721179794.691613:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TUSER_BITS_C to block PcieTop.AxiPcieCore.DmaObAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 16, bitSize 4, mode RO, verifyEn 1 lx 1721179794.691614:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TID_BITS_C to block PcieTop.AxiPcieCore.DmaObAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 12, bitSize 4, mode RO, verifyEn 1 lx 1721179794.691614:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TKEEP_MODE_C to block PcieTop.AxiPcieCore.DmaObAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 8, bitSize 4, mode RO, verifyEn 1 lx 1721179794.691614:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TUSER_MODE_C to block PcieTop.AxiPcieCore.DmaObAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 4, bitSize 4, mode RO, verifyEn 1 lx 1721179794.691615:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Adding variable AXIS_CONFIG_G_TSTRB_EN_C to block PcieTop.AxiPcieCore.DmaObAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 1, bitSize 1, mode RO, verifyEn 1 lx 1721179794.691615:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Adding variable COMMON_CLK_G to block PcieTop.AxiPcieCore.DmaObAxisMon.CntRst at offset 0x00000000, bitIdx=0, bitOffset 0, bitSize 1, mode RO, verifyEn 1 lx 1721179794.691616:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692004:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692009:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.VendorID: Starting logger with level = 10 1721179794.692010:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.VendorID: Adding variable VendorID to block PcieTop.AxiPcieCore.AxiPciePhy.VendorID at offset 0x00000000, bitIdx=0, bitOffset 0, bitSize 16, mode RO, verifyEn 1 lx 1721179794.692011:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.VendorID: Adding variable DeviceID to block PcieTop.AxiPcieCore.AxiPciePhy.VendorID at offset 0x00000000, bitIdx=0, bitOffset 16, bitSize 16, mode RO, verifyEn 1 lx 1721179794.692016:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.VendorID: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692021:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692024:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.Command: Starting logger with level = 10 1721179794.692025:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.Command: Adding variable Command to block PcieTop.AxiPcieCore.AxiPciePhy.Command at offset 0x00000004, bitIdx=0, bitOffset 0, bitSize 16, mode RO, verifyEn 1 lx 1721179794.692025:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.Command: Adding variable Status to block PcieTop.AxiPcieCore.AxiPciePhy.Command at offset 0x00000004, bitIdx=0, bitOffset 16, bitSize 16, mode RO, verifyEn 1 lx 1721179794.692026:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.Command: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692030:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692033:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.RevisionID: Starting logger with level = 10 1721179794.692033:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.RevisionID: Adding variable RevisionID to block PcieTop.AxiPcieCore.AxiPciePhy.RevisionID at offset 0x00000008, bitIdx=0, bitOffset 0, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692034:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.RevisionID: Adding variable ProgIF to block PcieTop.AxiPcieCore.AxiPciePhy.RevisionID at offset 0x00000008, bitIdx=0, bitOffset 8, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692034:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.RevisionID: Adding variable Subclass to block PcieTop.AxiPcieCore.AxiPciePhy.RevisionID at offset 0x00000008, bitIdx=0, bitOffset 16, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692034:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.RevisionID: Adding variable ClassCode to block PcieTop.AxiPcieCore.AxiPciePhy.RevisionID at offset 0x00000008, bitIdx=0, bitOffset 24, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692035:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.RevisionID: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692039:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692042:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize: Starting logger with level = 10 1721179794.692042:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize: Adding variable CacheLineSize to block PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize at offset 0x0000000c, bitIdx=0, bitOffset 0, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692043:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize: Adding variable LatencyTimer to block PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize at offset 0x0000000c, bitIdx=0, bitOffset 8, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692043:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize: Adding variable HeaderType to block PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize at offset 0x0000000c, bitIdx=0, bitOffset 16, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692043:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize: Adding variable BIST to block PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize at offset 0x0000000c, bitIdx=0, bitOffset 24, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692044:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692047:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692050:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[0]: Starting logger with level = 10 1721179794.692051:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[0]: Adding variable BaseAddressBar[0] to block PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[0] at offset 0x00000010, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.692053:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[0]: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692057:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692059:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[1]: Starting logger with level = 10 1721179794.692060:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[1]: Adding variable BaseAddressBar[1] to block PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[1] at offset 0x00000014, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.692060:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[1]: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692064:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692066:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[2]: Starting logger with level = 10 1721179794.692067:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[2]: Adding variable BaseAddressBar[2] to block PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[2] at offset 0x00000018, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.692067:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[2]: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692072:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692075:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[3]: Starting logger with level = 10 1721179794.692075:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[3]: Adding variable BaseAddressBar[3] to block PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[3] at offset 0x0000001c, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.692076:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[3]: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692079:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692081:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[4]: Starting logger with level = 10 1721179794.692082:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[4]: Adding variable BaseAddressBar[4] to block PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[4] at offset 0x00000020, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.692082:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[4]: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692086:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692088:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[5]: Starting logger with level = 10 1721179794.692089:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[5]: Adding variable BaseAddressBar[5] to block PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[5] at offset 0x00000024, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.692089:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[5]: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692092:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692095:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CardbusCisPointer: Starting logger with level = 10 1721179794.692095:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CardbusCisPointer: Adding variable CardbusCisPointer to block PcieTop.AxiPcieCore.AxiPciePhy.CardbusCisPointer at offset 0x00000028, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.692096:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CardbusCisPointer: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692099:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692115:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.SubVendorId: Starting logger with level = 10 1721179794.692118:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.SubVendorId: Adding variable SubVendorId to block PcieTop.AxiPcieCore.AxiPciePhy.SubVendorId at offset 0x0000002c, bitIdx=0, bitOffset 0, bitSize 16, mode RO, verifyEn 1 lx 1721179794.692119:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.SubVendorId: Adding variable SubDeviceId to block PcieTop.AxiPcieCore.AxiPciePhy.SubVendorId at offset 0x0000002c, bitIdx=0, bitOffset 16, bitSize 16, mode RO, verifyEn 1 lx 1721179794.692120:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.SubVendorId: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692123:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692134:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.ExpansionRomBaseAddress: Starting logger with level = 10 1721179794.692135:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.ExpansionRomBaseAddress: Adding variable ExpansionRomBaseAddress to block PcieTop.AxiPcieCore.AxiPciePhy.ExpansionRomBaseAddress at offset 0x00000030, bitIdx=0, bitOffset 0, bitSize 32, mode RO, verifyEn 1 lx 1721179794.692136:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.ExpansionRomBaseAddress: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692139:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692142:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CapabilitiesPointer: Starting logger with level = 10 1721179794.692142:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CapabilitiesPointer: Adding variable CapabilitiesPointer to block PcieTop.AxiPcieCore.AxiPciePhy.CapabilitiesPointer at offset 0x00000034, bitIdx=0, bitOffset 0, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692143:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CapabilitiesPointer: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692146:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692153:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine: Starting logger with level = 10 1721179794.692153:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine: Adding variable InterruptLine to block PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine at offset 0x0000003c, bitIdx=0, bitOffset 0, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692154:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine: Adding variable InterruptPin to block PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine at offset 0x0000003c, bitIdx=0, bitOffset 8, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692154:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine: Adding variable MinGrant to block PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine at offset 0x0000003c, bitIdx=0, bitOffset 16, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692154:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine: Adding variable MaxLatency to block PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine at offset 0x0000003c, bitIdx=0, bitOffset 24, bitSize 8, mode RO, verifyEn 1 lx 1721179794.692155:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692158:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692162:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Starting logger with level = 10 1721179794.692162:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=0, valueOffset=0, valueBits 8, mode RO, verifyEn 1 1721179794.692163:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=1, valueOffset=8, valueBits 8, mode RO, verifyEn 1 1721179794.692163:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=2, valueOffset=16, valueBits 8, mode RO, verifyEn 1 1721179794.692173:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=3, valueOffset=24, valueBits 8, mode RO, verifyEn 1 1721179794.692173:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=4, valueOffset=32, valueBits 8, mode RO, verifyEn 1 1721179794.692173:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=5, valueOffset=40, valueBits 8, mode RO, verifyEn 1 1721179794.692174:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=6, valueOffset=48, valueBits 8, mode RO, verifyEn 1 1721179794.692174:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=7, valueOffset=56, valueBits 8, mode RO, verifyEn 1 1721179794.692175:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=8, valueOffset=64, valueBits 8, mode RO, verifyEn 1 1721179794.692175:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=9, valueOffset=72, valueBits 8, mode RO, verifyEn 1 1721179794.692175:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=10, valueOffset=80, valueBits 8, mode RO, verifyEn 1 1721179794.692176:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=11, valueOffset=88, valueBits 8, mode RO, verifyEn 1 1721179794.692176:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=12, valueOffset=96, valueBits 8, mode RO, verifyEn 1 1721179794.692176:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=13, valueOffset=104, valueBits 8, mode RO, verifyEn 1 1721179794.692177:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=14, valueOffset=112, valueBits 8, mode RO, verifyEn 1 1721179794.692177:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=15, valueOffset=120, valueBits 8, mode RO, verifyEn 1 1721179794.692177:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=16, valueOffset=128, valueBits 8, mode RO, verifyEn 1 1721179794.692178:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=17, valueOffset=136, valueBits 8, mode RO, verifyEn 1 1721179794.692178:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=18, valueOffset=144, valueBits 8, mode RO, verifyEn 1 1721179794.692179:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=19, valueOffset=152, valueBits 8, mode RO, verifyEn 1 1721179794.692181:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=20, valueOffset=160, valueBits 8, mode RO, verifyEn 1 1721179794.692181:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=21, valueOffset=168, valueBits 8, mode RO, verifyEn 1 1721179794.692181:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=22, valueOffset=176, valueBits 8, mode RO, verifyEn 1 1721179794.692182:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=23, valueOffset=184, valueBits 8, mode RO, verifyEn 1 1721179794.692182:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=24, valueOffset=192, valueBits 8, mode RO, verifyEn 1 1721179794.692182:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=25, valueOffset=200, valueBits 8, mode RO, verifyEn 1 1721179794.692183:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=26, valueOffset=208, valueBits 8, mode RO, verifyEn 1 1721179794.692183:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=27, valueOffset=216, valueBits 8, mode RO, verifyEn 1 1721179794.692183:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=28, valueOffset=224, valueBits 8, mode RO, verifyEn 1 1721179794.692184:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=29, valueOffset=232, valueBits 8, mode RO, verifyEn 1 1721179794.692184:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=30, valueOffset=240, valueBits 8, mode RO, verifyEn 1 1721179794.692184:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=31, valueOffset=248, valueBits 8, mode RO, verifyEn 1 1721179794.692185:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=32, valueOffset=256, valueBits 8, mode RO, verifyEn 1 1721179794.692185:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=33, valueOffset=264, valueBits 8, mode RO, verifyEn 1 1721179794.692186:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=34, valueOffset=272, valueBits 8, mode RO, verifyEn 1 1721179794.692186:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=35, valueOffset=280, valueBits 8, mode RO, verifyEn 1 1721179794.692189:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=36, valueOffset=288, valueBits 8, mode RO, verifyEn 1 1721179794.692189:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=37, valueOffset=296, valueBits 8, mode RO, verifyEn 1 1721179794.692189:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=38, valueOffset=304, valueBits 8, mode RO, verifyEn 1 1721179794.692190:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=39, valueOffset=312, valueBits 8, mode RO, verifyEn 1 1721179794.692190:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=40, valueOffset=320, valueBits 8, mode RO, verifyEn 1 1721179794.692190:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=41, valueOffset=328, valueBits 8, mode RO, verifyEn 1 1721179794.692191:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=42, valueOffset=336, valueBits 8, mode RO, verifyEn 1 1721179794.692191:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=43, valueOffset=344, valueBits 8, mode RO, verifyEn 1 1721179794.692191:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=44, valueOffset=352, valueBits 8, mode RO, verifyEn 1 1721179794.692192:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=45, valueOffset=360, valueBits 8, mode RO, verifyEn 1 1721179794.692192:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=46, valueOffset=368, valueBits 8, mode RO, verifyEn 1 1721179794.692193:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=47, valueOffset=376, valueBits 8, mode RO, verifyEn 1 1721179794.692197:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=48, valueOffset=384, valueBits 8, mode RO, verifyEn 1 1721179794.692197:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=49, valueOffset=392, valueBits 8, mode RO, verifyEn 1 1721179794.692198:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=50, valueOffset=400, valueBits 8, mode RO, verifyEn 1 1721179794.692198:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=51, valueOffset=408, valueBits 8, mode RO, verifyEn 1 1721179794.692200:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=52, valueOffset=416, valueBits 8, mode RO, verifyEn 1 1721179794.692201:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=53, valueOffset=424, valueBits 8, mode RO, verifyEn 1 1721179794.692201:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=54, valueOffset=432, valueBits 8, mode RO, verifyEn 1 1721179794.692201:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=55, valueOffset=440, valueBits 8, mode RO, verifyEn 1 1721179794.692202:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=56, valueOffset=448, valueBits 8, mode RO, verifyEn 1 1721179794.692202:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=57, valueOffset=456, valueBits 8, mode RO, verifyEn 1 1721179794.692202:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=58, valueOffset=464, valueBits 8, mode RO, verifyEn 1 1721179794.692203:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=59, valueOffset=472, valueBits 8, mode RO, verifyEn 1 1721179794.692203:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=60, valueOffset=480, valueBits 8, mode RO, verifyEn 1 1721179794.692203:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=61, valueOffset=488, valueBits 8, mode RO, verifyEn 1 1721179794.692204:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=62, valueOffset=496, valueBits 8, mode RO, verifyEn 1 1721179794.692204:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=63, valueOffset=504, valueBits 8, mode RO, verifyEn 1 1721179794.692204:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=64, valueOffset=512, valueBits 8, mode RO, verifyEn 1 1721179794.692205:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=65, valueOffset=520, valueBits 8, mode RO, verifyEn 1 1721179794.692205:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=66, valueOffset=528, valueBits 8, mode RO, verifyEn 1 1721179794.692205:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=67, valueOffset=536, valueBits 8, mode RO, verifyEn 1 1721179794.692206:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=68, valueOffset=544, valueBits 8, mode RO, verifyEn 1 1721179794.692208:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=69, valueOffset=552, valueBits 8, mode RO, verifyEn 1 1721179794.692208:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=70, valueOffset=560, valueBits 8, mode RO, verifyEn 1 1721179794.692209:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=71, valueOffset=568, valueBits 8, mode RO, verifyEn 1 1721179794.692209:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=72, valueOffset=576, valueBits 8, mode RO, verifyEn 1 1721179794.692209:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=73, valueOffset=584, valueBits 8, mode RO, verifyEn 1 1721179794.692210:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=74, valueOffset=592, valueBits 8, mode RO, verifyEn 1 1721179794.692210:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=75, valueOffset=600, valueBits 8, mode RO, verifyEn 1 1721179794.692211:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=76, valueOffset=608, valueBits 8, mode RO, verifyEn 1 1721179794.692211:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=77, valueOffset=616, valueBits 8, mode RO, verifyEn 1 1721179794.692211:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=78, valueOffset=624, valueBits 8, mode RO, verifyEn 1 1721179794.692212:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=79, valueOffset=632, valueBits 8, mode RO, verifyEn 1 1721179794.692212:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=80, valueOffset=640, valueBits 8, mode RO, verifyEn 1 1721179794.692212:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=81, valueOffset=648, valueBits 8, mode RO, verifyEn 1 1721179794.692213:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=82, valueOffset=656, valueBits 8, mode RO, verifyEn 1 1721179794.692213:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=83, valueOffset=664, valueBits 8, mode RO, verifyEn 1 1721179794.692213:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=84, valueOffset=672, valueBits 8, mode RO, verifyEn 1 1721179794.692215:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=85, valueOffset=680, valueBits 8, mode RO, verifyEn 1 1721179794.692216:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=86, valueOffset=688, valueBits 8, mode RO, verifyEn 1 1721179794.692216:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=87, valueOffset=696, valueBits 8, mode RO, verifyEn 1 1721179794.692216:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=88, valueOffset=704, valueBits 8, mode RO, verifyEn 1 1721179794.692217:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=89, valueOffset=712, valueBits 8, mode RO, verifyEn 1 1721179794.692217:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=90, valueOffset=720, valueBits 8, mode RO, verifyEn 1 1721179794.692217:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=91, valueOffset=728, valueBits 8, mode RO, verifyEn 1 1721179794.692218:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=92, valueOffset=736, valueBits 8, mode RO, verifyEn 1 1721179794.692218:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=93, valueOffset=744, valueBits 8, mode RO, verifyEn 1 1721179794.692218:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=94, valueOffset=752, valueBits 8, mode RO, verifyEn 1 1721179794.692219:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=95, valueOffset=760, valueBits 8, mode RO, verifyEn 1 1721179794.692219:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=96, valueOffset=768, valueBits 8, mode RO, verifyEn 1 1721179794.692220:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=97, valueOffset=776, valueBits 8, mode RO, verifyEn 1 1721179794.692220:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=98, valueOffset=784, valueBits 8, mode RO, verifyEn 1 1721179794.692220:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=99, valueOffset=792, valueBits 8, mode RO, verifyEn 1 1721179794.692221:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=100, valueOffset=800, valueBits 8, mode RO, verifyEn 1 1721179794.692223:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=101, valueOffset=808, valueBits 8, mode RO, verifyEn 1 1721179794.692223:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=102, valueOffset=816, valueBits 8, mode RO, verifyEn 1 1721179794.692223:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=103, valueOffset=824, valueBits 8, mode RO, verifyEn 1 1721179794.692224:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=104, valueOffset=832, valueBits 8, mode RO, verifyEn 1 1721179794.692224:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=105, valueOffset=840, valueBits 8, mode RO, verifyEn 1 1721179794.692225:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=106, valueOffset=848, valueBits 8, mode RO, verifyEn 1 1721179794.692225:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=107, valueOffset=856, valueBits 8, mode RO, verifyEn 1 1721179794.692225:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=108, valueOffset=864, valueBits 8, mode RO, verifyEn 1 1721179794.692226:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=109, valueOffset=872, valueBits 8, mode RO, verifyEn 1 1721179794.692226:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=110, valueOffset=880, valueBits 8, mode RO, verifyEn 1 1721179794.692226:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=111, valueOffset=888, valueBits 8, mode RO, verifyEn 1 1721179794.692231:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=112, valueOffset=896, valueBits 8, mode RO, verifyEn 1 1721179794.692231:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=113, valueOffset=904, valueBits 8, mode RO, verifyEn 1 1721179794.692232:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=114, valueOffset=912, valueBits 8, mode RO, verifyEn 1 1721179794.692232:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=115, valueOffset=920, valueBits 8, mode RO, verifyEn 1 1721179794.692232:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=116, valueOffset=928, valueBits 8, mode RO, verifyEn 1 1721179794.692234:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=117, valueOffset=936, valueBits 8, mode RO, verifyEn 1 1721179794.692235:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=118, valueOffset=944, valueBits 8, mode RO, verifyEn 1 1721179794.692235:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=119, valueOffset=952, valueBits 8, mode RO, verifyEn 1 1721179794.692236:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=120, valueOffset=960, valueBits 8, mode RO, verifyEn 1 1721179794.692236:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=121, valueOffset=968, valueBits 8, mode RO, verifyEn 1 1721179794.692236:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=122, valueOffset=976, valueBits 8, mode RO, verifyEn 1 1721179794.692237:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=123, valueOffset=984, valueBits 8, mode RO, verifyEn 1 1721179794.692237:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=124, valueOffset=992, valueBits 8, mode RO, verifyEn 1 1721179794.692237:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=125, valueOffset=1000, valueBits 8, mode RO, verifyEn 1 1721179794.692238:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=126, valueOffset=1008, valueBits 8, mode RO, verifyEn 1 1721179794.692238:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=127, valueOffset=1016, valueBits 8, mode RO, verifyEn 1 1721179794.692238:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=128, valueOffset=1024, valueBits 8, mode RO, verifyEn 1 1721179794.692239:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=129, valueOffset=1032, valueBits 8, mode RO, verifyEn 1 1721179794.692239:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=130, valueOffset=1040, valueBits 8, mode RO, verifyEn 1 1721179794.692240:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=131, valueOffset=1048, valueBits 8, mode RO, verifyEn 1 1721179794.692240:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=132, valueOffset=1056, valueBits 8, mode RO, verifyEn 1 1721179794.692240:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=133, valueOffset=1064, valueBits 8, mode RO, verifyEn 1 1721179794.692242:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=134, valueOffset=1072, valueBits 8, mode RO, verifyEn 1 1721179794.692243:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=135, valueOffset=1080, valueBits 8, mode RO, verifyEn 1 1721179794.692251:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=136, valueOffset=1088, valueBits 8, mode RO, verifyEn 1 1721179794.692251:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=137, valueOffset=1096, valueBits 8, mode RO, verifyEn 1 1721179794.692252:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=138, valueOffset=1104, valueBits 8, mode RO, verifyEn 1 1721179794.692252:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=139, valueOffset=1112, valueBits 8, mode RO, verifyEn 1 1721179794.692252:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=140, valueOffset=1120, valueBits 8, mode RO, verifyEn 1 1721179794.692253:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=141, valueOffset=1128, valueBits 8, mode RO, verifyEn 1 1721179794.692253:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=142, valueOffset=1136, valueBits 8, mode RO, verifyEn 1 1721179794.692253:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=143, valueOffset=1144, valueBits 8, mode RO, verifyEn 1 1721179794.692254:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=144, valueOffset=1152, valueBits 8, mode RO, verifyEn 1 1721179794.692254:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=145, valueOffset=1160, valueBits 8, mode RO, verifyEn 1 1721179794.692254:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=146, valueOffset=1168, valueBits 8, mode RO, verifyEn 1 1721179794.692255:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=147, valueOffset=1176, valueBits 8, mode RO, verifyEn 1 1721179794.692255:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=148, valueOffset=1184, valueBits 8, mode RO, verifyEn 1 1721179794.692256:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=149, valueOffset=1192, valueBits 8, mode RO, verifyEn 1 1721179794.692258:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=150, valueOffset=1200, valueBits 8, mode RO, verifyEn 1 1721179794.692258:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=151, valueOffset=1208, valueBits 8, mode RO, verifyEn 1 1721179794.692259:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=152, valueOffset=1216, valueBits 8, mode RO, verifyEn 1 1721179794.692259:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=153, valueOffset=1224, valueBits 8, mode RO, verifyEn 1 1721179794.692259:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=154, valueOffset=1232, valueBits 8, mode RO, verifyEn 1 1721179794.692260:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=155, valueOffset=1240, valueBits 8, mode RO, verifyEn 1 1721179794.692260:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=156, valueOffset=1248, valueBits 8, mode RO, verifyEn 1 1721179794.692261:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=157, valueOffset=1256, valueBits 8, mode RO, verifyEn 1 1721179794.692261:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=158, valueOffset=1264, valueBits 8, mode RO, verifyEn 1 1721179794.692261:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=159, valueOffset=1272, valueBits 8, mode RO, verifyEn 1 1721179794.692262:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=160, valueOffset=1280, valueBits 8, mode RO, verifyEn 1 1721179794.692262:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=161, valueOffset=1288, valueBits 8, mode RO, verifyEn 1 1721179794.692262:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=162, valueOffset=1296, valueBits 8, mode RO, verifyEn 1 1721179794.692263:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=163, valueOffset=1304, valueBits 8, mode RO, verifyEn 1 1721179794.692263:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=164, valueOffset=1312, valueBits 8, mode RO, verifyEn 1 1721179794.692263:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=165, valueOffset=1320, valueBits 8, mode RO, verifyEn 1 1721179794.692266:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=166, valueOffset=1328, valueBits 8, mode RO, verifyEn 1 1721179794.692266:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=167, valueOffset=1336, valueBits 8, mode RO, verifyEn 1 1721179794.692266:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=168, valueOffset=1344, valueBits 8, mode RO, verifyEn 1 1721179794.692267:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=169, valueOffset=1352, valueBits 8, mode RO, verifyEn 1 1721179794.692267:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=170, valueOffset=1360, valueBits 8, mode RO, verifyEn 1 1721179794.692267:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=171, valueOffset=1368, valueBits 8, mode RO, verifyEn 1 1721179794.692268:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=172, valueOffset=1376, valueBits 8, mode RO, verifyEn 1 1721179794.692268:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=173, valueOffset=1384, valueBits 8, mode RO, verifyEn 1 1721179794.692268:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=174, valueOffset=1392, valueBits 8, mode RO, verifyEn 1 1721179794.692269:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=175, valueOffset=1400, valueBits 8, mode RO, verifyEn 1 1721179794.692269:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=176, valueOffset=1408, valueBits 8, mode RO, verifyEn 1 1721179794.692270:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=177, valueOffset=1416, valueBits 8, mode RO, verifyEn 1 1721179794.692271:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=178, valueOffset=1424, valueBits 8, mode RO, verifyEn 1 1721179794.692271:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=179, valueOffset=1432, valueBits 8, mode RO, verifyEn 1 1721179794.692271:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=180, valueOffset=1440, valueBits 8, mode RO, verifyEn 1 1721179794.692272:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=181, valueOffset=1448, valueBits 8, mode RO, verifyEn 1 1721179794.692274:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=182, valueOffset=1456, valueBits 8, mode RO, verifyEn 1 1721179794.692274:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=183, valueOffset=1464, valueBits 8, mode RO, verifyEn 1 1721179794.692274:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=184, valueOffset=1472, valueBits 8, mode RO, verifyEn 1 1721179794.692275:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=185, valueOffset=1480, valueBits 8, mode RO, verifyEn 1 1721179794.692275:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=186, valueOffset=1488, valueBits 8, mode RO, verifyEn 1 1721179794.692275:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=187, valueOffset=1496, valueBits 8, mode RO, verifyEn 1 1721179794.692276:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=188, valueOffset=1504, valueBits 8, mode RO, verifyEn 1 1721179794.692276:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=189, valueOffset=1512, valueBits 8, mode RO, verifyEn 1 1721179794.692276:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=190, valueOffset=1520, valueBits 8, mode RO, verifyEn 1 1721179794.692277:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Adding variable DevSpecRegion to block PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion at offset 0x00000040, index=191, valueOffset=1528, valueBits 8, mode RO, verifyEn 1 1721179794.692278:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 000 - 009: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692279:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 010 - 019: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692290:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 020 - 029: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692290:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 030 - 039: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692291:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 040 - 049: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692292:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 050 - 059: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692293:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 060 - 069: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692293:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 070 - 079: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692294:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 080 - 089: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692297:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 090 - 099: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692298:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 100 - 109: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692298:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 110 - 119: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692299:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 120 - 129: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692300:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 130 - 139: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692300:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 140 - 149: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692301:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 150 - 159: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692302:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 160 - 169: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692303:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 170 - 179: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692303:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 180 - 189: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692304:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Done adding variables. Verify Mask 190 - 191: 0x00 0x00 1721179794.692500:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692520:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.DataWrBus: Starting logger with level = 10 1721179794.692521:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.DataWrBus: Adding variable DataWrBus to block PcieTop.AxiPcieCore.AxiMicronMt28ew.DataWrBus at offset 0x00000000, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.692522:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.DataWrBus: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692539:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692542:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.AddrBus: Starting logger with level = 10 1721179794.692542:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.AddrBus: Adding variable AddrBus to block PcieTop.AxiPcieCore.AxiMicronMt28ew.AddrBus at offset 0x00000004, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.692543:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.AddrBus: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692547:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692549:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.DataRdBus: Starting logger with level = 10 1721179794.692550:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.DataRdBus: Adding variable DataRdBus to block PcieTop.AxiPcieCore.AxiMicronMt28ew.DataRdBus at offset 0x00000008, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.692551:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.DataRdBus: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692554:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692572:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.TranSize: Starting logger with level = 10 1721179794.692572:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.TranSize: Adding variable TranSize to block PcieTop.AxiPcieCore.AxiMicronMt28ew.TranSize at offset 0x00000080, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.692576:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.TranSize: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692580:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692583:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstTran: Starting logger with level = 10 1721179794.692583:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstTran: Adding variable BurstTran to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstTran at offset 0x00000084, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.692584:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstTran: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.692587:pyrogue.memory.Master: Starting logger with level = 10 1721179794.692593:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Starting logger with level = 10 1721179794.692593:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=0, valueOffset=0, valueBits 32, mode RW, verifyEn 0 1721179794.692594:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=1, valueOffset=32, valueBits 32, mode RW, verifyEn 0 1721179794.692594:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=2, valueOffset=64, valueBits 32, mode RW, verifyEn 0 1721179794.692595:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=3, valueOffset=96, valueBits 32, mode RW, verifyEn 0 1721179794.692595:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=4, valueOffset=128, valueBits 32, mode RW, verifyEn 0 1721179794.692595:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=5, valueOffset=160, valueBits 32, mode RW, verifyEn 0 1721179794.692596:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=6, valueOffset=192, valueBits 32, mode RW, verifyEn 0 1721179794.692596:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=7, valueOffset=224, valueBits 32, mode RW, verifyEn 0 1721179794.692596:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=8, valueOffset=256, valueBits 32, mode RW, verifyEn 0 1721179794.692597:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=9, valueOffset=288, valueBits 32, mode RW, verifyEn 0 1721179794.692597:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=10, valueOffset=320, valueBits 32, mode RW, verifyEn 0 1721179794.692598:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=11, valueOffset=352, valueBits 32, mode RW, verifyEn 0 1721179794.692602:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=12, valueOffset=384, valueBits 32, mode RW, verifyEn 0 1721179794.692603:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=13, valueOffset=416, valueBits 32, mode RW, verifyEn 0 1721179794.692603:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=14, valueOffset=448, valueBits 32, mode RW, verifyEn 0 1721179794.692604:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=15, valueOffset=480, valueBits 32, mode RW, verifyEn 0 1721179794.692604:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=16, valueOffset=512, valueBits 32, mode RW, verifyEn 0 1721179794.692604:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=17, valueOffset=544, valueBits 32, mode RW, verifyEn 0 1721179794.692605:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=18, valueOffset=576, valueBits 32, mode RW, verifyEn 0 1721179794.692605:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=19, valueOffset=608, valueBits 32, mode RW, verifyEn 0 1721179794.692605:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=20, valueOffset=640, valueBits 32, mode RW, verifyEn 0 1721179794.692606:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=21, valueOffset=672, valueBits 32, mode RW, verifyEn 0 1721179794.692606:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=22, valueOffset=704, valueBits 32, mode RW, verifyEn 0 1721179794.692606:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=23, valueOffset=736, valueBits 32, mode RW, verifyEn 0 1721179794.692607:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=24, valueOffset=768, valueBits 32, mode RW, verifyEn 0 1721179794.692607:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=25, valueOffset=800, valueBits 32, mode RW, verifyEn 0 1721179794.692608:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=26, valueOffset=832, valueBits 32, mode RW, verifyEn 0 1721179794.692608:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=27, valueOffset=864, valueBits 32, mode RW, verifyEn 0 1721179794.692608:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=28, valueOffset=896, valueBits 32, mode RW, verifyEn 0 1721179794.692611:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=29, valueOffset=928, valueBits 32, mode RW, verifyEn 0 1721179794.692611:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=30, valueOffset=960, valueBits 32, mode RW, verifyEn 0 1721179794.692611:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=31, valueOffset=992, valueBits 32, mode RW, verifyEn 0 1721179794.692612:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=32, valueOffset=1024, valueBits 32, mode RW, verifyEn 0 1721179794.692612:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=33, valueOffset=1056, valueBits 32, mode RW, verifyEn 0 1721179794.692612:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=34, valueOffset=1088, valueBits 32, mode RW, verifyEn 0 1721179794.692613:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=35, valueOffset=1120, valueBits 32, mode RW, verifyEn 0 1721179794.692613:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=36, valueOffset=1152, valueBits 32, mode RW, verifyEn 0 1721179794.692614:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=37, valueOffset=1184, valueBits 32, mode RW, verifyEn 0 1721179794.692614:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=38, valueOffset=1216, valueBits 32, mode RW, verifyEn 0 1721179794.692614:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=39, valueOffset=1248, valueBits 32, mode RW, verifyEn 0 1721179794.692615:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=40, valueOffset=1280, valueBits 32, mode RW, verifyEn 0 1721179794.692615:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=41, valueOffset=1312, valueBits 32, mode RW, verifyEn 0 1721179794.692615:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=42, valueOffset=1344, valueBits 32, mode RW, verifyEn 0 1721179794.692616:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=43, valueOffset=1376, valueBits 32, mode RW, verifyEn 0 1721179794.692616:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=44, valueOffset=1408, valueBits 32, mode RW, verifyEn 0 1721179794.692618:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=45, valueOffset=1440, valueBits 32, mode RW, verifyEn 0 1721179794.692618:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=46, valueOffset=1472, valueBits 32, mode RW, verifyEn 0 1721179794.692619:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=47, valueOffset=1504, valueBits 32, mode RW, verifyEn 0 1721179794.692619:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=48, valueOffset=1536, valueBits 32, mode RW, verifyEn 0 1721179794.692620:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=49, valueOffset=1568, valueBits 32, mode RW, verifyEn 0 1721179794.692620:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=50, valueOffset=1600, valueBits 32, mode RW, verifyEn 0 1721179794.692620:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=51, valueOffset=1632, valueBits 32, mode RW, verifyEn 0 1721179794.692621:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=52, valueOffset=1664, valueBits 32, mode RW, verifyEn 0 1721179794.692621:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=53, valueOffset=1696, valueBits 32, mode RW, verifyEn 0 1721179794.692621:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=54, valueOffset=1728, valueBits 32, mode RW, verifyEn 0 1721179794.692622:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=55, valueOffset=1760, valueBits 32, mode RW, verifyEn 0 1721179794.692622:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=56, valueOffset=1792, valueBits 32, mode RW, verifyEn 0 1721179794.692622:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=57, valueOffset=1824, valueBits 32, mode RW, verifyEn 0 1721179794.692623:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=58, valueOffset=1856, valueBits 32, mode RW, verifyEn 0 1721179794.692623:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=59, valueOffset=1888, valueBits 32, mode RW, verifyEn 0 1721179794.692624:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=60, valueOffset=1920, valueBits 32, mode RW, verifyEn 0 1721179794.692633:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=61, valueOffset=1952, valueBits 32, mode RW, verifyEn 0 1721179794.692633:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=62, valueOffset=1984, valueBits 32, mode RW, verifyEn 0 1721179794.692634:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=63, valueOffset=2016, valueBits 32, mode RW, verifyEn 0 1721179794.692634:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=64, valueOffset=2048, valueBits 32, mode RW, verifyEn 0 1721179794.692634:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=65, valueOffset=2080, valueBits 32, mode RW, verifyEn 0 1721179794.692635:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=66, valueOffset=2112, valueBits 32, mode RW, verifyEn 0 1721179794.692635:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=67, valueOffset=2144, valueBits 32, mode RW, verifyEn 0 1721179794.692635:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=68, valueOffset=2176, valueBits 32, mode RW, verifyEn 0 1721179794.692636:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=69, valueOffset=2208, valueBits 32, mode RW, verifyEn 0 1721179794.692636:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=70, valueOffset=2240, valueBits 32, mode RW, verifyEn 0 1721179794.692636:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=71, valueOffset=2272, valueBits 32, mode RW, verifyEn 0 1721179794.692637:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=72, valueOffset=2304, valueBits 32, mode RW, verifyEn 0 1721179794.692637:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=73, valueOffset=2336, valueBits 32, mode RW, verifyEn 0 1721179794.692638:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=74, valueOffset=2368, valueBits 32, mode RW, verifyEn 0 1721179794.692638:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=75, valueOffset=2400, valueBits 32, mode RW, verifyEn 0 1721179794.692638:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=76, valueOffset=2432, valueBits 32, mode RW, verifyEn 0 1721179794.692639:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=77, valueOffset=2464, valueBits 32, mode RW, verifyEn 0 1721179794.692641:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=78, valueOffset=2496, valueBits 32, mode RW, verifyEn 0 1721179794.692642:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=79, valueOffset=2528, valueBits 32, mode RW, verifyEn 0 1721179794.692642:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=80, valueOffset=2560, valueBits 32, mode RW, verifyEn 0 1721179794.692642:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=81, valueOffset=2592, valueBits 32, mode RW, verifyEn 0 1721179794.692643:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=82, valueOffset=2624, valueBits 32, mode RW, verifyEn 0 1721179794.692643:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=83, valueOffset=2656, valueBits 32, mode RW, verifyEn 0 1721179794.692643:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=84, valueOffset=2688, valueBits 32, mode RW, verifyEn 0 1721179794.692644:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=85, valueOffset=2720, valueBits 32, mode RW, verifyEn 0 1721179794.692644:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=86, valueOffset=2752, valueBits 32, mode RW, verifyEn 0 1721179794.692645:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=87, valueOffset=2784, valueBits 32, mode RW, verifyEn 0 1721179794.692645:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=88, valueOffset=2816, valueBits 32, mode RW, verifyEn 0 1721179794.692645:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=89, valueOffset=2848, valueBits 32, mode RW, verifyEn 0 1721179794.692646:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=90, valueOffset=2880, valueBits 32, mode RW, verifyEn 0 1721179794.692646:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=91, valueOffset=2912, valueBits 32, mode RW, verifyEn 0 1721179794.692646:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=92, valueOffset=2944, valueBits 32, mode RW, verifyEn 0 1721179794.692647:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=93, valueOffset=2976, valueBits 32, mode RW, verifyEn 0 1721179794.692649:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=94, valueOffset=3008, valueBits 32, mode RW, verifyEn 0 1721179794.692649:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=95, valueOffset=3040, valueBits 32, mode RW, verifyEn 0 1721179794.692650:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=96, valueOffset=3072, valueBits 32, mode RW, verifyEn 0 1721179794.692650:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=97, valueOffset=3104, valueBits 32, mode RW, verifyEn 0 1721179794.692650:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=98, valueOffset=3136, valueBits 32, mode RW, verifyEn 0 1721179794.692657:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=99, valueOffset=3168, valueBits 32, mode RW, verifyEn 0 1721179794.692657:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=100, valueOffset=3200, valueBits 32, mode RW, verifyEn 0 1721179794.692657:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=101, valueOffset=3232, valueBits 32, mode RW, verifyEn 0 1721179794.692658:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=102, valueOffset=3264, valueBits 32, mode RW, verifyEn 0 1721179794.692658:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=103, valueOffset=3296, valueBits 32, mode RW, verifyEn 0 1721179794.692658:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=104, valueOffset=3328, valueBits 32, mode RW, verifyEn 0 1721179794.692659:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=105, valueOffset=3360, valueBits 32, mode RW, verifyEn 0 1721179794.692659:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=106, valueOffset=3392, valueBits 32, mode RW, verifyEn 0 1721179794.692660:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=107, valueOffset=3424, valueBits 32, mode RW, verifyEn 0 1721179794.692660:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=108, valueOffset=3456, valueBits 32, mode RW, verifyEn 0 1721179794.692660:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=109, valueOffset=3488, valueBits 32, mode RW, verifyEn 0 1721179794.692663:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=110, valueOffset=3520, valueBits 32, mode RW, verifyEn 0 1721179794.692663:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=111, valueOffset=3552, valueBits 32, mode RW, verifyEn 0 1721179794.692663:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=112, valueOffset=3584, valueBits 32, mode RW, verifyEn 0 1721179794.692664:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=113, valueOffset=3616, valueBits 32, mode RW, verifyEn 0 1721179794.692664:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=114, valueOffset=3648, valueBits 32, mode RW, verifyEn 0 1721179794.692664:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=115, valueOffset=3680, valueBits 32, mode RW, verifyEn 0 1721179794.692665:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=116, valueOffset=3712, valueBits 32, mode RW, verifyEn 0 1721179794.692665:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=117, valueOffset=3744, valueBits 32, mode RW, verifyEn 0 1721179794.692665:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=118, valueOffset=3776, valueBits 32, mode RW, verifyEn 0 1721179794.692666:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=119, valueOffset=3808, valueBits 32, mode RW, verifyEn 0 1721179794.692666:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=120, valueOffset=3840, valueBits 32, mode RW, verifyEn 0 1721179794.692666:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=121, valueOffset=3872, valueBits 32, mode RW, verifyEn 0 1721179794.692667:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=122, valueOffset=3904, valueBits 32, mode RW, verifyEn 0 1721179794.692667:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=123, valueOffset=3936, valueBits 32, mode RW, verifyEn 0 1721179794.692668:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=124, valueOffset=3968, valueBits 32, mode RW, verifyEn 0 1721179794.692668:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=125, valueOffset=4000, valueBits 32, mode RW, verifyEn 0 1721179794.692668:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=126, valueOffset=4032, valueBits 32, mode RW, verifyEn 0 1721179794.692678:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=127, valueOffset=4064, valueBits 32, mode RW, verifyEn 0 1721179794.692678:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=128, valueOffset=4096, valueBits 32, mode RW, verifyEn 0 1721179794.692679:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=129, valueOffset=4128, valueBits 32, mode RW, verifyEn 0 1721179794.692679:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=130, valueOffset=4160, valueBits 32, mode RW, verifyEn 0 1721179794.692680:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=131, valueOffset=4192, valueBits 32, mode RW, verifyEn 0 1721179794.692680:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=132, valueOffset=4224, valueBits 32, mode RW, verifyEn 0 1721179794.692680:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=133, valueOffset=4256, valueBits 32, mode RW, verifyEn 0 1721179794.692681:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=134, valueOffset=4288, valueBits 32, mode RW, verifyEn 0 1721179794.692681:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=135, valueOffset=4320, valueBits 32, mode RW, verifyEn 0 1721179794.692681:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=136, valueOffset=4352, valueBits 32, mode RW, verifyEn 0 1721179794.692682:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=137, valueOffset=4384, valueBits 32, mode RW, verifyEn 0 1721179794.692682:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=138, valueOffset=4416, valueBits 32, mode RW, verifyEn 0 1721179794.692682:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=139, valueOffset=4448, valueBits 32, mode RW, verifyEn 0 1721179794.692683:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=140, valueOffset=4480, valueBits 32, mode RW, verifyEn 0 1721179794.692683:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=141, valueOffset=4512, valueBits 32, mode RW, verifyEn 0 1721179794.692683:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=142, valueOffset=4544, valueBits 32, mode RW, verifyEn 0 1721179794.692704:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=143, valueOffset=4576, valueBits 32, mode RW, verifyEn 0 1721179794.692704:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=144, valueOffset=4608, valueBits 32, mode RW, verifyEn 0 1721179794.692705:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=145, valueOffset=4640, valueBits 32, mode RW, verifyEn 0 1721179794.692705:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=146, valueOffset=4672, valueBits 32, mode RW, verifyEn 0 1721179794.692706:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=147, valueOffset=4704, valueBits 32, mode RW, verifyEn 0 1721179794.692706:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=148, valueOffset=4736, valueBits 32, mode RW, verifyEn 0 1721179794.692706:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=149, valueOffset=4768, valueBits 32, mode RW, verifyEn 0 1721179794.692707:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=150, valueOffset=4800, valueBits 32, mode RW, verifyEn 0 1721179794.692707:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=151, valueOffset=4832, valueBits 32, mode RW, verifyEn 0 1721179794.692707:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=152, valueOffset=4864, valueBits 32, mode RW, verifyEn 0 1721179794.692708:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=153, valueOffset=4896, valueBits 32, mode RW, verifyEn 0 1721179794.692708:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=154, valueOffset=4928, valueBits 32, mode RW, verifyEn 0 1721179794.692708:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=155, valueOffset=4960, valueBits 32, mode RW, verifyEn 0 1721179794.692709:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=156, valueOffset=4992, valueBits 32, mode RW, verifyEn 0 1721179794.692709:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=157, valueOffset=5024, valueBits 32, mode RW, verifyEn 0 1721179794.692709:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=158, valueOffset=5056, valueBits 32, mode RW, verifyEn 0 1721179794.692712:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=159, valueOffset=5088, valueBits 32, mode RW, verifyEn 0 1721179794.692712:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=160, valueOffset=5120, valueBits 32, mode RW, verifyEn 0 1721179794.692713:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=161, valueOffset=5152, valueBits 32, mode RW, verifyEn 0 1721179794.692713:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=162, valueOffset=5184, valueBits 32, mode RW, verifyEn 0 1721179794.692713:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=163, valueOffset=5216, valueBits 32, mode RW, verifyEn 0 1721179794.692714:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=164, valueOffset=5248, valueBits 32, mode RW, verifyEn 0 1721179794.692714:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=165, valueOffset=5280, valueBits 32, mode RW, verifyEn 0 1721179794.692714:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=166, valueOffset=5312, valueBits 32, mode RW, verifyEn 0 1721179794.692715:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=167, valueOffset=5344, valueBits 32, mode RW, verifyEn 0 1721179794.692715:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=168, valueOffset=5376, valueBits 32, mode RW, verifyEn 0 1721179794.692716:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=169, valueOffset=5408, valueBits 32, mode RW, verifyEn 0 1721179794.692716:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=170, valueOffset=5440, valueBits 32, mode RW, verifyEn 0 1721179794.692716:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=171, valueOffset=5472, valueBits 32, mode RW, verifyEn 0 1721179794.692717:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=172, valueOffset=5504, valueBits 32, mode RW, verifyEn 0 1721179794.692717:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=173, valueOffset=5536, valueBits 32, mode RW, verifyEn 0 1721179794.692717:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=174, valueOffset=5568, valueBits 32, mode RW, verifyEn 0 1721179794.692721:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=175, valueOffset=5600, valueBits 32, mode RW, verifyEn 0 1721179794.692722:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=176, valueOffset=5632, valueBits 32, mode RW, verifyEn 0 1721179794.692722:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=177, valueOffset=5664, valueBits 32, mode RW, verifyEn 0 1721179794.692722:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=178, valueOffset=5696, valueBits 32, mode RW, verifyEn 0 1721179794.692723:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=179, valueOffset=5728, valueBits 32, mode RW, verifyEn 0 1721179794.692723:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=180, valueOffset=5760, valueBits 32, mode RW, verifyEn 0 1721179794.692731:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=181, valueOffset=5792, valueBits 32, mode RW, verifyEn 0 1721179794.692732:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=182, valueOffset=5824, valueBits 32, mode RW, verifyEn 0 1721179794.692732:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=183, valueOffset=5856, valueBits 32, mode RW, verifyEn 0 1721179794.692733:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=184, valueOffset=5888, valueBits 32, mode RW, verifyEn 0 1721179794.692733:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=185, valueOffset=5920, valueBits 32, mode RW, verifyEn 0 1721179794.692733:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=186, valueOffset=5952, valueBits 32, mode RW, verifyEn 0 1721179794.692734:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=187, valueOffset=5984, valueBits 32, mode RW, verifyEn 0 1721179794.692734:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=188, valueOffset=6016, valueBits 32, mode RW, verifyEn 0 1721179794.692734:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=189, valueOffset=6048, valueBits 32, mode RW, verifyEn 0 1721179794.692735:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=190, valueOffset=6080, valueBits 32, mode RW, verifyEn 0 1721179794.692735:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=191, valueOffset=6112, valueBits 32, mode RW, verifyEn 0 1721179794.692737:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=192, valueOffset=6144, valueBits 32, mode RW, verifyEn 0 1721179794.692738:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=193, valueOffset=6176, valueBits 32, mode RW, verifyEn 0 1721179794.692738:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=194, valueOffset=6208, valueBits 32, mode RW, verifyEn 0 1721179794.692738:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=195, valueOffset=6240, valueBits 32, mode RW, verifyEn 0 1721179794.692739:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=196, valueOffset=6272, valueBits 32, mode RW, verifyEn 0 1721179794.692739:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=197, valueOffset=6304, valueBits 32, mode RW, verifyEn 0 1721179794.692739:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=198, valueOffset=6336, valueBits 32, mode RW, verifyEn 0 1721179794.692740:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=199, valueOffset=6368, valueBits 32, mode RW, verifyEn 0 1721179794.692740:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=200, valueOffset=6400, valueBits 32, mode RW, verifyEn 0 1721179794.692740:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=201, valueOffset=6432, valueBits 32, mode RW, verifyEn 0 1721179794.692741:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=202, valueOffset=6464, valueBits 32, mode RW, verifyEn 0 1721179794.692741:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=203, valueOffset=6496, valueBits 32, mode RW, verifyEn 0 1721179794.692742:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=204, valueOffset=6528, valueBits 32, mode RW, verifyEn 0 1721179794.692742:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=205, valueOffset=6560, valueBits 32, mode RW, verifyEn 0 1721179794.692742:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=206, valueOffset=6592, valueBits 32, mode RW, verifyEn 0 1721179794.692743:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=207, valueOffset=6624, valueBits 32, mode RW, verifyEn 0 1721179794.692745:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=208, valueOffset=6656, valueBits 32, mode RW, verifyEn 0 1721179794.692745:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=209, valueOffset=6688, valueBits 32, mode RW, verifyEn 0 1721179794.692745:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=210, valueOffset=6720, valueBits 32, mode RW, verifyEn 0 1721179794.692746:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=211, valueOffset=6752, valueBits 32, mode RW, verifyEn 0 1721179794.692746:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=212, valueOffset=6784, valueBits 32, mode RW, verifyEn 0 1721179794.692747:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=213, valueOffset=6816, valueBits 32, mode RW, verifyEn 0 1721179794.692747:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=214, valueOffset=6848, valueBits 32, mode RW, verifyEn 0 1721179794.692747:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=215, valueOffset=6880, valueBits 32, mode RW, verifyEn 0 1721179794.692748:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=216, valueOffset=6912, valueBits 32, mode RW, verifyEn 0 1721179794.692748:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=217, valueOffset=6944, valueBits 32, mode RW, verifyEn 0 1721179794.692748:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=218, valueOffset=6976, valueBits 32, mode RW, verifyEn 0 1721179794.692749:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=219, valueOffset=7008, valueBits 32, mode RW, verifyEn 0 1721179794.692749:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=220, valueOffset=7040, valueBits 32, mode RW, verifyEn 0 1721179794.692749:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=221, valueOffset=7072, valueBits 32, mode RW, verifyEn 0 1721179794.692750:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=222, valueOffset=7104, valueBits 32, mode RW, verifyEn 0 1721179794.692750:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=223, valueOffset=7136, valueBits 32, mode RW, verifyEn 0 1721179794.692758:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=224, valueOffset=7168, valueBits 32, mode RW, verifyEn 0 1721179794.692759:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=225, valueOffset=7200, valueBits 32, mode RW, verifyEn 0 1721179794.692759:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=226, valueOffset=7232, valueBits 32, mode RW, verifyEn 0 1721179794.692759:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=227, valueOffset=7264, valueBits 32, mode RW, verifyEn 0 1721179794.692760:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=228, valueOffset=7296, valueBits 32, mode RW, verifyEn 0 1721179794.692763:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=229, valueOffset=7328, valueBits 32, mode RW, verifyEn 0 1721179794.692764:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=230, valueOffset=7360, valueBits 32, mode RW, verifyEn 0 1721179794.692764:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=231, valueOffset=7392, valueBits 32, mode RW, verifyEn 0 1721179794.692764:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=232, valueOffset=7424, valueBits 32, mode RW, verifyEn 0 1721179794.692765:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=233, valueOffset=7456, valueBits 32, mode RW, verifyEn 0 1721179794.692765:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=234, valueOffset=7488, valueBits 32, mode RW, verifyEn 0 1721179794.692766:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=235, valueOffset=7520, valueBits 32, mode RW, verifyEn 0 1721179794.692766:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=236, valueOffset=7552, valueBits 32, mode RW, verifyEn 0 1721179794.692766:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=237, valueOffset=7584, valueBits 32, mode RW, verifyEn 0 1721179794.692767:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=238, valueOffset=7616, valueBits 32, mode RW, verifyEn 0 1721179794.692767:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=239, valueOffset=7648, valueBits 32, mode RW, verifyEn 0 1721179794.692769:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=240, valueOffset=7680, valueBits 32, mode RW, verifyEn 0 1721179794.692770:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=241, valueOffset=7712, valueBits 32, mode RW, verifyEn 0 1721179794.692770:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=242, valueOffset=7744, valueBits 32, mode RW, verifyEn 0 1721179794.692770:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=243, valueOffset=7776, valueBits 32, mode RW, verifyEn 0 1721179794.692771:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=244, valueOffset=7808, valueBits 32, mode RW, verifyEn 0 1721179794.692771:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=245, valueOffset=7840, valueBits 32, mode RW, verifyEn 0 1721179794.692771:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=246, valueOffset=7872, valueBits 32, mode RW, verifyEn 0 1721179794.692772:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=247, valueOffset=7904, valueBits 32, mode RW, verifyEn 0 1721179794.692772:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=248, valueOffset=7936, valueBits 32, mode RW, verifyEn 0 1721179794.692772:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=249, valueOffset=7968, valueBits 32, mode RW, verifyEn 0 1721179794.692773:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=250, valueOffset=8000, valueBits 32, mode RW, verifyEn 0 1721179794.692773:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=251, valueOffset=8032, valueBits 32, mode RW, verifyEn 0 1721179794.692773:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=252, valueOffset=8064, valueBits 32, mode RW, verifyEn 0 1721179794.692774:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=253, valueOffset=8096, valueBits 32, mode RW, verifyEn 0 1721179794.692778:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=254, valueOffset=8128, valueBits 32, mode RW, verifyEn 0 1721179794.692778:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Adding variable BurstData to block PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData at offset 0x00000400, index=255, valueOffset=8160, valueBits 32, mode RW, verifyEn 0 1721179794.692780:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 000 - 009: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692783:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 010 - 019: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692783:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 020 - 029: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692784:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 030 - 039: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692785:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 040 - 049: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692786:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 050 - 059: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692786:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 060 - 069: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692787:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 070 - 079: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692788:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 080 - 089: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692789:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 090 - 099: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692789:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 100 - 109: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692790:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 110 - 119: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692791:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 120 - 129: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692792:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 130 - 139: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692792:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 140 - 149: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692793:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 150 - 159: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692794:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 160 - 169: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692794:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 170 - 179: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692795:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 180 - 189: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692796:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 190 - 199: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692797:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 200 - 209: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692797:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 210 - 219: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692798:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 220 - 229: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692801:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 230 - 239: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692811:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 240 - 249: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692812:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 250 - 259: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692813:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 260 - 269: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692813:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 270 - 279: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692814:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 280 - 289: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692815:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 290 - 299: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692816:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 300 - 309: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692816:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 310 - 319: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692817:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 320 - 329: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692818:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 330 - 339: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692818:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 340 - 349: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692819:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 350 - 359: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692820:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 360 - 369: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692821:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 370 - 379: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692821:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 380 - 389: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692822:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 390 - 399: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692823:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 400 - 409: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692823:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 410 - 419: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692824:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 420 - 429: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692825:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 430 - 439: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692825:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 440 - 449: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692828:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 450 - 459: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692832:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 460 - 469: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692833:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 470 - 479: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692834:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 480 - 489: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692834:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 490 - 499: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692835:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 500 - 509: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692836:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 510 - 519: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692837:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 520 - 529: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692837:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 530 - 539: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692838:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 540 - 549: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692839:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 550 - 559: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692839:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 560 - 569: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692840:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 570 - 579: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692841:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 580 - 589: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692842:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 590 - 599: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692842:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 600 - 609: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692843:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 610 - 619: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692844:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 620 - 629: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692844:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 630 - 639: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692845:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 640 - 649: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692846:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 650 - 659: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692846:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 660 - 669: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692847:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 670 - 679: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692850:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 680 - 689: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692851:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 690 - 699: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692851:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 700 - 709: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692852:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 710 - 719: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692853:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 720 - 729: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692853:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 730 - 739: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692854:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 740 - 749: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692855:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 750 - 759: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692855:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 760 - 769: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692856:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 770 - 779: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692857:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 780 - 789: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692858:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 790 - 799: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692858:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 800 - 809: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692859:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 810 - 819: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692860:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 820 - 829: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692860:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 830 - 839: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692861:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 840 - 849: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692862:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 850 - 859: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692863:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 860 - 869: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692863:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 870 - 879: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692864:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 880 - 889: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692865:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 890 - 899: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692879:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 900 - 909: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692880:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 910 - 919: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692880:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 920 - 929: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692881:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 930 - 939: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692882:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 940 - 949: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692883:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 950 - 959: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692883:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 960 - 969: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692884:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 970 - 979: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692885:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 980 - 989: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692885:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 990 - 999: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692886:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 1000 - 1009: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692887:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 1010 - 1019: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.692887:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Done adding variables. Verify Mask 1020 - 1023: 0x00 0x00 0x00 0x00 1721179794.693066:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693085:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].PasswordLock: Starting logger with level = 10 1721179794.693086:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].PasswordLock: Adding variable PasswordLock to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].PasswordLock at offset 0x00000000, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.693087:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].PasswordLock: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.693092:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693103:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].ModeReg: Starting logger with level = 10 1721179794.693104:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].ModeReg: Adding variable ModeReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].ModeReg at offset 0x00000004, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.693104:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].ModeReg: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.693108:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693110:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Starting logger with level = 10 1721179794.693111:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Adding variable AddrReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg at offset 0x00000008, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.693112:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.693117:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693120:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Starting logger with level = 10 1721179794.693128:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Adding variable CmdReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg at offset 0x0000000c, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.693129:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.693132:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693135:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Starting logger with level = 10 1721179794.693136:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=0, valueOffset=0, valueBits 32, mode RW, verifyEn 0 1721179794.693136:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=1, valueOffset=32, valueBits 32, mode RW, verifyEn 0 1721179794.693137:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=2, valueOffset=64, valueBits 32, mode RW, verifyEn 0 1721179794.693137:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=3, valueOffset=96, valueBits 32, mode RW, verifyEn 0 1721179794.693137:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=4, valueOffset=128, valueBits 32, mode RW, verifyEn 0 1721179794.693138:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=5, valueOffset=160, valueBits 32, mode RW, verifyEn 0 1721179794.693138:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=6, valueOffset=192, valueBits 32, mode RW, verifyEn 0 1721179794.693139:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=7, valueOffset=224, valueBits 32, mode RW, verifyEn 0 1721179794.693139:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=8, valueOffset=256, valueBits 32, mode RW, verifyEn 0 1721179794.693139:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=9, valueOffset=288, valueBits 32, mode RW, verifyEn 0 1721179794.693140:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=10, valueOffset=320, valueBits 32, mode RW, verifyEn 0 1721179794.693140:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=11, valueOffset=352, valueBits 32, mode RW, verifyEn 0 1721179794.693140:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=12, valueOffset=384, valueBits 32, mode RW, verifyEn 0 1721179794.693141:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=13, valueOffset=416, valueBits 32, mode RW, verifyEn 0 1721179794.693143:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=14, valueOffset=448, valueBits 32, mode RW, verifyEn 0 1721179794.693143:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=15, valueOffset=480, valueBits 32, mode RW, verifyEn 0 1721179794.693144:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=16, valueOffset=512, valueBits 32, mode RW, verifyEn 0 1721179794.693144:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=17, valueOffset=544, valueBits 32, mode RW, verifyEn 0 1721179794.693144:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=18, valueOffset=576, valueBits 32, mode RW, verifyEn 0 1721179794.693145:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=19, valueOffset=608, valueBits 32, mode RW, verifyEn 0 1721179794.693145:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=20, valueOffset=640, valueBits 32, mode RW, verifyEn 0 1721179794.693146:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=21, valueOffset=672, valueBits 32, mode RW, verifyEn 0 1721179794.693154:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=22, valueOffset=704, valueBits 32, mode RW, verifyEn 0 1721179794.693155:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=23, valueOffset=736, valueBits 32, mode RW, verifyEn 0 1721179794.693155:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=24, valueOffset=768, valueBits 32, mode RW, verifyEn 0 1721179794.693155:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=25, valueOffset=800, valueBits 32, mode RW, verifyEn 0 1721179794.693156:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=26, valueOffset=832, valueBits 32, mode RW, verifyEn 0 1721179794.693156:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=27, valueOffset=864, valueBits 32, mode RW, verifyEn 0 1721179794.693156:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=28, valueOffset=896, valueBits 32, mode RW, verifyEn 0 1721179794.693157:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=29, valueOffset=928, valueBits 32, mode RW, verifyEn 0 1721179794.693159:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=30, valueOffset=960, valueBits 32, mode RW, verifyEn 0 1721179794.693160:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=31, valueOffset=992, valueBits 32, mode RW, verifyEn 0 1721179794.693160:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=32, valueOffset=1024, valueBits 32, mode RW, verifyEn 0 1721179794.693161:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=33, valueOffset=1056, valueBits 32, mode RW, verifyEn 0 1721179794.693161:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=34, valueOffset=1088, valueBits 32, mode RW, verifyEn 0 1721179794.693161:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=35, valueOffset=1120, valueBits 32, mode RW, verifyEn 0 1721179794.693162:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=36, valueOffset=1152, valueBits 32, mode RW, verifyEn 0 1721179794.693162:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=37, valueOffset=1184, valueBits 32, mode RW, verifyEn 0 1721179794.693162:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=38, valueOffset=1216, valueBits 32, mode RW, verifyEn 0 1721179794.693163:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=39, valueOffset=1248, valueBits 32, mode RW, verifyEn 0 1721179794.693163:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=40, valueOffset=1280, valueBits 32, mode RW, verifyEn 0 1721179794.693164:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=41, valueOffset=1312, valueBits 32, mode RW, verifyEn 0 1721179794.693164:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=42, valueOffset=1344, valueBits 32, mode RW, verifyEn 0 1721179794.693164:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=43, valueOffset=1376, valueBits 32, mode RW, verifyEn 0 1721179794.693165:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=44, valueOffset=1408, valueBits 32, mode RW, verifyEn 0 1721179794.693165:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=45, valueOffset=1440, valueBits 32, mode RW, verifyEn 0 1721179794.693165:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=46, valueOffset=1472, valueBits 32, mode RW, verifyEn 0 1721179794.693167:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=47, valueOffset=1504, valueBits 32, mode RW, verifyEn 0 1721179794.693168:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=48, valueOffset=1536, valueBits 32, mode RW, verifyEn 0 1721179794.693168:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=49, valueOffset=1568, valueBits 32, mode RW, verifyEn 0 1721179794.693169:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=50, valueOffset=1600, valueBits 32, mode RW, verifyEn 0 1721179794.693169:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=51, valueOffset=1632, valueBits 32, mode RW, verifyEn 0 1721179794.693169:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=52, valueOffset=1664, valueBits 32, mode RW, verifyEn 0 1721179794.693170:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=53, valueOffset=1696, valueBits 32, mode RW, verifyEn 0 1721179794.693170:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=54, valueOffset=1728, valueBits 32, mode RW, verifyEn 0 1721179794.693170:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=55, valueOffset=1760, valueBits 32, mode RW, verifyEn 0 1721179794.693171:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=56, valueOffset=1792, valueBits 32, mode RW, verifyEn 0 1721179794.693171:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=57, valueOffset=1824, valueBits 32, mode RW, verifyEn 0 1721179794.693171:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=58, valueOffset=1856, valueBits 32, mode RW, verifyEn 0 1721179794.693172:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=59, valueOffset=1888, valueBits 32, mode RW, verifyEn 0 1721179794.693172:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=60, valueOffset=1920, valueBits 32, mode RW, verifyEn 0 1721179794.693173:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=61, valueOffset=1952, valueBits 32, mode RW, verifyEn 0 1721179794.693173:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=62, valueOffset=1984, valueBits 32, mode RW, verifyEn 0 1721179794.693173:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg at offset 0x00000200, index=63, valueOffset=2016, valueBits 32, mode RW, verifyEn 0 1721179794.693187:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 000 - 009: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693188:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 010 - 019: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693189:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 020 - 029: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693190:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 030 - 039: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693190:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 040 - 049: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693191:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 050 - 059: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693192:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 060 - 069: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693193:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 070 - 079: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693193:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 080 - 089: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693194:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 090 - 099: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693195:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 100 - 109: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693196:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 110 - 119: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693196:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 120 - 129: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693197:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 130 - 139: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693198:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 140 - 149: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693198:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 150 - 159: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693199:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 160 - 169: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693200:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 170 - 179: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693201:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 180 - 189: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693201:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 190 - 199: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693202:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 200 - 209: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693203:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 210 - 219: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693208:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 220 - 229: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693209:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 230 - 239: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693209:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 240 - 249: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693210:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Done adding variables. Verify Mask 250 - 255: 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693347:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693352:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].PasswordLock: Starting logger with level = 10 1721179794.693353:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].PasswordLock: Adding variable PasswordLock to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].PasswordLock at offset 0x00000000, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.693354:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].PasswordLock: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.693373:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693376:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].ModeReg: Starting logger with level = 10 1721179794.693376:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].ModeReg: Adding variable ModeReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].ModeReg at offset 0x00000004, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.693377:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].ModeReg: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.693381:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693383:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].AddrReg: Starting logger with level = 10 1721179794.693384:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].AddrReg: Adding variable AddrReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].AddrReg at offset 0x00000008, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.693385:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].AddrReg: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.693392:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693395:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].CmdReg: Starting logger with level = 10 1721179794.693395:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].CmdReg: Adding variable CmdReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].CmdReg at offset 0x0000000c, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 0 lx 1721179794.693396:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].CmdReg: Done adding variables. Verify Mask 000 - 003: 0x00 0x00 0x00 0x00 1721179794.693399:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693402:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Starting logger with level = 10 1721179794.693402:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=0, valueOffset=0, valueBits 32, mode RW, verifyEn 0 1721179794.693403:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=1, valueOffset=32, valueBits 32, mode RW, verifyEn 0 1721179794.693403:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=2, valueOffset=64, valueBits 32, mode RW, verifyEn 0 1721179794.693406:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=3, valueOffset=96, valueBits 32, mode RW, verifyEn 0 1721179794.693406:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=4, valueOffset=128, valueBits 32, mode RW, verifyEn 0 1721179794.693407:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=5, valueOffset=160, valueBits 32, mode RW, verifyEn 0 1721179794.693407:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=6, valueOffset=192, valueBits 32, mode RW, verifyEn 0 1721179794.693407:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=7, valueOffset=224, valueBits 32, mode RW, verifyEn 0 1721179794.693408:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=8, valueOffset=256, valueBits 32, mode RW, verifyEn 0 1721179794.693408:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=9, valueOffset=288, valueBits 32, mode RW, verifyEn 0 1721179794.693408:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=10, valueOffset=320, valueBits 32, mode RW, verifyEn 0 1721179794.693409:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=11, valueOffset=352, valueBits 32, mode RW, verifyEn 0 1721179794.693409:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=12, valueOffset=384, valueBits 32, mode RW, verifyEn 0 1721179794.693410:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=13, valueOffset=416, valueBits 32, mode RW, verifyEn 0 1721179794.693410:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=14, valueOffset=448, valueBits 32, mode RW, verifyEn 0 1721179794.693410:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=15, valueOffset=480, valueBits 32, mode RW, verifyEn 0 1721179794.693411:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=16, valueOffset=512, valueBits 32, mode RW, verifyEn 0 1721179794.693411:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=17, valueOffset=544, valueBits 32, mode RW, verifyEn 0 1721179794.693411:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=18, valueOffset=576, valueBits 32, mode RW, verifyEn 0 1721179794.693412:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=19, valueOffset=608, valueBits 32, mode RW, verifyEn 0 1721179794.693414:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=20, valueOffset=640, valueBits 32, mode RW, verifyEn 0 1721179794.693415:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=21, valueOffset=672, valueBits 32, mode RW, verifyEn 0 1721179794.693415:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=22, valueOffset=704, valueBits 32, mode RW, verifyEn 0 1721179794.693415:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=23, valueOffset=736, valueBits 32, mode RW, verifyEn 0 1721179794.693416:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=24, valueOffset=768, valueBits 32, mode RW, verifyEn 0 1721179794.693416:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=25, valueOffset=800, valueBits 32, mode RW, verifyEn 0 1721179794.693416:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=26, valueOffset=832, valueBits 32, mode RW, verifyEn 0 1721179794.693417:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=27, valueOffset=864, valueBits 32, mode RW, verifyEn 0 1721179794.693417:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=28, valueOffset=896, valueBits 32, mode RW, verifyEn 0 1721179794.693418:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=29, valueOffset=928, valueBits 32, mode RW, verifyEn 0 1721179794.693418:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=30, valueOffset=960, valueBits 32, mode RW, verifyEn 0 1721179794.693418:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=31, valueOffset=992, valueBits 32, mode RW, verifyEn 0 1721179794.693419:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=32, valueOffset=1024, valueBits 32, mode RW, verifyEn 0 1721179794.693419:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=33, valueOffset=1056, valueBits 32, mode RW, verifyEn 0 1721179794.693419:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=34, valueOffset=1088, valueBits 32, mode RW, verifyEn 0 1721179794.693420:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=35, valueOffset=1120, valueBits 32, mode RW, verifyEn 0 1721179794.693420:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=36, valueOffset=1152, valueBits 32, mode RW, verifyEn 0 1721179794.693423:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=37, valueOffset=1184, valueBits 32, mode RW, verifyEn 0 1721179794.693423:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=38, valueOffset=1216, valueBits 32, mode RW, verifyEn 0 1721179794.693423:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=39, valueOffset=1248, valueBits 32, mode RW, verifyEn 0 1721179794.693424:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=40, valueOffset=1280, valueBits 32, mode RW, verifyEn 0 1721179794.693424:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=41, valueOffset=1312, valueBits 32, mode RW, verifyEn 0 1721179794.693424:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=42, valueOffset=1344, valueBits 32, mode RW, verifyEn 0 1721179794.693425:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=43, valueOffset=1376, valueBits 32, mode RW, verifyEn 0 1721179794.693425:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=44, valueOffset=1408, valueBits 32, mode RW, verifyEn 0 1721179794.693425:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=45, valueOffset=1440, valueBits 32, mode RW, verifyEn 0 1721179794.693426:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=46, valueOffset=1472, valueBits 32, mode RW, verifyEn 0 1721179794.693426:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=47, valueOffset=1504, valueBits 32, mode RW, verifyEn 0 1721179794.693427:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=48, valueOffset=1536, valueBits 32, mode RW, verifyEn 0 1721179794.693427:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=49, valueOffset=1568, valueBits 32, mode RW, verifyEn 0 1721179794.693427:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=50, valueOffset=1600, valueBits 32, mode RW, verifyEn 0 1721179794.693428:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=51, valueOffset=1632, valueBits 32, mode RW, verifyEn 0 1721179794.693428:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=52, valueOffset=1664, valueBits 32, mode RW, verifyEn 0 1721179794.693430:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=53, valueOffset=1696, valueBits 32, mode RW, verifyEn 0 1721179794.693430:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=54, valueOffset=1728, valueBits 32, mode RW, verifyEn 0 1721179794.693440:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=55, valueOffset=1760, valueBits 32, mode RW, verifyEn 0 1721179794.693440:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=56, valueOffset=1792, valueBits 32, mode RW, verifyEn 0 1721179794.693440:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=57, valueOffset=1824, valueBits 32, mode RW, verifyEn 0 1721179794.693441:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=58, valueOffset=1856, valueBits 32, mode RW, verifyEn 0 1721179794.693441:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=59, valueOffset=1888, valueBits 32, mode RW, verifyEn 0 1721179794.693441:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=60, valueOffset=1920, valueBits 32, mode RW, verifyEn 0 1721179794.693442:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=61, valueOffset=1952, valueBits 32, mode RW, verifyEn 0 1721179794.693442:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=62, valueOffset=1984, valueBits 32, mode RW, verifyEn 0 1721179794.693442:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Adding variable DataReg to block PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg at offset 0x00000200, index=63, valueOffset=2016, valueBits 32, mode RW, verifyEn 0 1721179794.693444:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 000 - 009: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693444:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 010 - 019: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693445:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 020 - 029: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693453:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 030 - 039: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693454:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 040 - 049: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693455:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 050 - 059: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693455:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 060 - 069: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693456:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 070 - 079: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693459:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 080 - 089: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693460:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 090 - 099: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693461:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 100 - 109: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693461:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 110 - 119: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693462:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 120 - 129: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693463:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 130 - 139: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693464:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 140 - 149: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693464:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 150 - 159: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693465:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 160 - 169: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693466:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 170 - 179: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693466:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 180 - 189: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693467:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 190 - 199: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693468:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 200 - 209: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693469:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 210 - 219: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693469:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 220 - 229: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693470:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 230 - 239: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693471:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 240 - 249: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693471:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Done adding variables. Verify Mask 250 - 255: 0x00 0x00 0x00 0x00 0x00 0x00 1721179794.693640:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693653:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Rnw: Starting logger with level = 10 1721179794.693654:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Rnw: Adding variable Rnw to block PcieTop.AxiPcieCore.AxilBridge.Regs.Rnw at offset 0x00000000, bitIdx=0, bitOffset 0, bitSize 1, mode RW, verifyEn 1 lx 1721179794.693665:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Rnw: Done adding variables. Verify Mask 000 - 003: 0x01 0x00 0x00 0x00 1721179794.693670:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693675:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridgeBasedir = /afs/slac.stanford.edu/u/re/ruckman/projects/pgp-pcie-apps/firmware/submodules/axi-pcie-core/scripts WARNING: PcieTop.AxiPcieCore.numDmaLanes = 1 != PcieTop.AxiPcieCore.AxiVersion.DMA_SIZE_G = 2 .Regs.Done: Starting logger with level = 10 1721179794.693679:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Done: Adding variable Done to block PcieTop.AxiPcieCore.AxilBridge.Regs.Done at offset 0x00000004, bitIdx=0, bitOffset 0, bitSize 1, mode RO, verifyEn 1 lx 1721179794.693680:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Done: Adding variable Resp to block PcieTop.AxiPcieCore.AxilBridge.Regs.Done at offset 0x00000004, bitIdx=0, bitOffset 1, bitSize 2, mode RW, verifyEn 1 lx 1721179794.693681:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Done: Done adding variables. Verify Mask 000 - 003: 0x06 0x00 0x00 0x00 1721179794.693688:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693691:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Addr: Starting logger with level = 10 1721179794.693691:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Addr: Adding variable Addr to block PcieTop.AxiPcieCore.AxilBridge.Regs.Addr at offset 0x00000008, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 1 lx 1721179794.693692:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Addr: Done adding variables. Verify Mask 000 - 003: 0xff 0xff 0xff 0xff 1721179794.693696:pyrogue.memory.Master: Starting logger with level = 10 1721179794.693698:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Data: Starting logger with level = 10 1721179794.693699:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Data: Adding variable Data to block PcieTop.AxiPcieCore.AxilBridge.Regs.Data at offset 0x0000000c, bitIdx=0, bitOffset 0, bitSize 32, mode RW, verifyEn 1 lx 1721179794.693699:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Data: Done adding variables. Verify Mask 000 - 003: 0xff 0xff 0xff 0xff 1721179794.695478:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_SIZE_G: Start transaction type = 1, Offset=0x400, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695481:pyrogue.memory.Master: Request transaction type=1 id=1 1721179794.695482:pyrogue.memory.Transaction: Created transaction type=1 id=1, address=0x0000000000000400, size=4 1721179794.695540:pyrogue.axi.AxiMemMap: Transaction id=1, addr 0x0000000000020400. Size=4, type=1, data=0x00000002 1721179794.695542:pyrogue.memory.Transaction: Transaction done. type=1 id=1, address=0x0000000000020400, size=4 1721179794.695550:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_SIZE_G: Transaction complete 1721179794.695651:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.PCIE_HW_TYPE_G: Start transaction type = 1, Offset=0x424, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695652:pyrogue.memory.Master: Request transaction type=1 id=2 1721179794.695652:pyrogue.memory.Transaction: Created transaction type=1 id=2, address=0x0000000000000424, size=4 1721179794.695678:pyrogue.axi.AxiMemMap: Transaction id=2, addr 0x0000000000020424. Size=4, type=1, data=0x00000016 1721179794.695680:pyrogue.memory.Transaction: Transaction done. type=1 id=2, address=0x0000000000020424, size=4 1721179794.695687:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.PCIE_HW_TYPE_G: Transaction complete 1721179794.695874:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaVersion: Start transaction type = 1, Offset=0x0, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695876:pyrogue.memory.Master: Request transaction type=1 id=3 1721179794.695876:pyrogue.memory.Transaction: Created transaction type=1 id=3, address=0x0000000000000000, size=4 1721179794.695920:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.ScratchPad: Start transaction type = 1, Offset=0x4, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695921:pyrogue.memory.Master: Request transaction type=1 id=4 1721179794.695922:pyrogue.memory.Transaction: Created transaction type=1 id=4, address=0x0000000000000004, size=4 1721179794.695923:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UpTimeCnt: Start transaction type = 1, Offset=0x8, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695924:pyrogue.memory.Master: Request transaction type=1 id=5 1721179794.695924:pyrogue.memory.Transaction: Created transaction type=1 id=5, address=0x0000000000000008, size=4 1721179794.695929:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReloadHalt: Start transaction type = 1, Offset=0x100, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695930:pyrogue.memory.Master: Request transaction type=1 id=6 1721179794.695930:pyrogue.memory.Transaction: Created transaction type=1 id=6, address=0x0000000000000100, size=4 1721179794.695932:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReloadAddress: Start transaction type = 1, Offset=0x108, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695933:pyrogue.memory.Master: Request transaction type=1 id=7 1721179794.695933:pyrogue.memory.Transaction: Created transaction type=1 id=7, address=0x0000000000000108, size=4 1721179794.695939:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UserReset: Start transaction type = 1, Offset=0x10c, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695940:pyrogue.memory.Master: Request transaction type=1 id=8 1721179794.695940:pyrogue.memory.Transaction: Created transaction type=1 id=8, address=0x000000000000010c, size=4 1721179794.695942:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FdSerial: Start transaction type = 1, Offset=0x300, lByte=0, hByte=7, tOff=0x0, tSize=8 1721179794.695942:pyrogue.memory.Master: Request transaction type=1 id=9 1721179794.695942:pyrogue.axi.AxiMemMap: Transaction id=3, addr 0x0000000000020000. Size=4, type=1, data=0x33882112 1721179794.695946:pyrogue.memory.Transaction: Transaction done. type=1 id=3, address=0x0000000000020000, size=4 1721179794.695943:pyrogue.memory.Transaction: Created transaction type=1 id=9, address=0x0000000000000300, size=8 1721179794.695949:pyrogue.axi.AxiMemMap: Transaction id=4, addr 0x0000000000020004. Size=4, type=1, data=0x00000000 1721179794.695952:pyrogue.memory.Transaction: Transaction done. type=1 id=4, address=0x0000000000020004, size=4 1721179794.695950:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_SIZE_G: Start transaction type = 1, Offset=0x400, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695955:pyrogue.axi.AxiMemMap: Transaction id=5, addr 0x0000000000020008. Size=4, type=1, data=0x00000181 1721179794.695957:pyrogue.memory.Transaction: Transaction done. type=1 id=5, address=0x0000000000020008, size=4 1721179794.695955:pyrogue.memory.Master: Request transaction type=1 id=10 1721179794.695960:pyrogue.axi.AxiMemMap: Transaction id=6, addr 0x0000000000020100. Size=4, type=1, data=0x00000000 1721179794.695962:pyrogue.memory.Transaction: Transaction done. type=1 id=6, address=0x0000000000020100, size=4 1721179794.695960:pyrogue.memory.Transaction: Created transaction type=1 id=10, address=0x0000000000000400, size=4 1721179794.695966:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.Reserved: Start transaction type = 1, Offset=0x404, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695967:pyrogue.memory.Master: Request transaction type=1 id=11 1721179794.695967:pyrogue.memory.Transaction: Created transaction type=1 id=11, address=0x0000000000000404, size=4 1721179794.695969:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DRIVER_TYPE_ID_G: Start transaction type = 1, Offset=0x408, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.695969:pyrogue.axi.AxiMemMap: Transaction id=7, addr 0x0000000000020108. Size=4, type=1, data=0x00000000 1721179794.695970:pyrogue.memory.Master: Request transaction type=1 id=12 1721179794.695971:pyrogue.memory.Transaction: Transaction done. type=1 id=7, address=0x0000000000020108, size=4 1721179794.695974:pyrogue.axi.AxiMemMap: Transaction id=8, addr 0x000000000002010c. Size=4, type=1, data=0x00000000 1721179794.695977:pyrogue.memory.Transaction: Transaction done. type=1 id=8, address=0x000000000002010c, size=4 1721179794.695971:pyrogue.memory.Transaction: Created transaction type=1 id=12, address=0x0000000000000408, size=4 1721179794.695980:pyrogue.axi.AxiMemMap: Transaction id=9, addr 0x0000000000020300. Size=8, type=1, data=0x00000000 1721179794.695980:pyrogue.memory.Transaction: Transaction done. type=1 id=9, address=0x0000000000020300, size=8 1721179794.695990:pyrogue.axi.AxiMemMap: Transaction id=10, addr 0x0000000000020400. Size=4, type=1, data=0x00000002 1721179794.695992:pyrogue.memory.Transaction: Transaction done. type=1 id=10, address=0x0000000000020400, size=4 1721179794.695994:pyrogue.axi.AxiMemMap: Transaction id=11, addr 0x0000000000020404. Size=4, type=1, data=0x00000001 1721179794.695995:pyrogue.memory.Transaction: Transaction done. type=1 id=11, address=0x0000000000020404, size=4 1721179794.695997:pyrogue.axi.AxiMemMap: Transaction id=12, addr 0x0000000000020408. Size=4, type=1, data=0x00000000 1721179794.695998:pyrogue.memory.Transaction: Transaction done. type=1 id=12, address=0x0000000000020408, size=4 1721179794.695981:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.XIL_DEVICE_G: Start transaction type = 1, Offset=0x40c, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696009:pyrogue.memory.Master: Request transaction type=1 id=13 1721179794.696010:pyrogue.memory.Transaction: Created transaction type=1 id=13, address=0x000000000000040c, size=4 1721179794.696013:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_CLK_FREQ_C: Start transaction type = 1, Offset=0x410, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696014:pyrogue.memory.Master: Request transaction type=1 id=14 1721179794.696014:pyrogue.memory.Transaction: Created transaction type=1 id=14, address=0x0000000000000410, size=4 1721179794.696016:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BOOT_PROM_G: Start transaction type = 1, Offset=0x414, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696017:pyrogue.memory.Master: Request transaction type=1 id=15 1721179794.696017:pyrogue.memory.Transaction: Created transaction type=1 id=15, address=0x0000000000000414, size=4 1721179794.696019:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Start transaction type = 1, Offset=0x418, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696019:pyrogue.axi.AxiMemMap: Transaction id=13, addr 0x000000000002040c. Size=4, type=1, data=0x00000000 1721179794.696020:pyrogue.memory.Master: Request transaction type=1 id=16 1721179794.696021:pyrogue.memory.Transaction: Transaction done. type=1 id=13, address=0x000000000002040c, size=4 1721179794.696022:pyrogue.memory.Transaction: Created transaction type=1 id=16, address=0x0000000000000418, size=4 1721179794.696026:pyrogue.axi.AxiMemMap: Transaction id=14, addr 0x0000000000020410. Size=4, type=1, data=0x250000000 1721179794.696026:pyrogue.memory.Transaction: Transaction done. type=1 id=14, address=0x0000000000020410, size=4 1721179794.696029:pyrogue.axi.AxiMemMap: Transaction id=15, addr 0x0000000000020414. Size=4, type=1, data=0x00000002 1721179794.696029:pyrogue.memory.Transaction: Transaction done. type=1 id=15, address=0x0000000000020414, size=4 1721179794.696031:pyrogue.axi.AxiMemMap: Transaction id=16, addr 0x0000000000020418. Size=4, type=1, data=0x1082274064 1721179794.696032:pyrogue.memory.Transaction: Transaction done. type=1 id=16, address=0x0000000000020418, size=4 1721179794.696032:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C: Start transaction type = 1, Offset=0x41c, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696033:pyrogue.memory.Master: Request transaction type=1 id=17 1721179794.696033:pyrogue.memory.Transaction: Created transaction type=1 id=17, address=0x000000000000041c, size=4 1721179794.696036:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AppClkFreq: Start transaction type = 1, Offset=0x420, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696037:pyrogue.memory.Master: Request transaction type=1 id=18 1721179794.696038:pyrogue.memory.Transaction: Created transaction type=1 id=18, address=0x0000000000000420, size=4 1721179794.696040:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.PCIE_HW_TYPE_G: Start transaction type = 1, Offset=0x424, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696040:pyrogue.memory.Master: Request transaction type=1 id=19 1721179794.696041:pyrogue.memory.Transaction: Created transaction type=1 id=19, address=0x0000000000000424, size=4 1721179794.696047:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceId: Start transaction type = 1, Offset=0x500, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696047:pyrogue.memory.Master: Request transaction type=1 id=20 1721179794.696040:pyrogue.axi.AxiMemMap: Transaction id=17, addr 0x000000000002041c. Size=4, type=1, data=0x675283976 1721179794.696054:pyrogue.memory.Transaction: Transaction done. type=1 id=17, address=0x000000000002041c, size=4 1721179794.696054:pyrogue.memory.Transaction: Created transaction type=1 id=20, address=0x0000000000000500, size=4 1721179794.696056:pyrogue.axi.AxiMemMap: Transaction id=18, addr 0x0000000000020420. Size=4, type=1, data=0x156545502 1721179794.696057:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.GitHash: Start transaction type = 1, Offset=0x600, lByte=0, hByte=19, tOff=0x0, tSize=20 1721179794.696057:pyrogue.memory.Transaction: Transaction done. type=1 id=18, address=0x0000000000020420, size=4 1721179794.696062:pyrogue.axi.AxiMemMap: Transaction id=19, addr 0x0000000000020424. Size=4, type=1, data=0x00000016 1721179794.696058:pyrogue.memory.Master: Request transaction type=1 id=21 1721179794.696062:pyrogue.memory.Transaction: Transaction done. type=1 id=19, address=0x0000000000020424, size=4 1721179794.696063:pyrogue.memory.Transaction: Created transaction type=1 id=21, address=0x0000000000000600, size=20 1721179794.696066:pyrogue.axi.AxiMemMap: Transaction id=20, addr 0x0000000000020500. Size=4, type=1, data=0x00000000 1721179794.696068:pyrogue.memory.Transaction: Transaction done. type=1 id=20, address=0x0000000000020500, size=4 1721179794.696066:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceDna: Start transaction type = 1, Offset=0x700, lByte=0, hByte=15, tOff=0x0, tSize=16 1721179794.696075:pyrogue.memory.Master: Request transaction type=1 id=22 1721179794.696075:pyrogue.axi.AxiMemMap: Transaction id=21, addr 0x0000000000020600. Size=20, type=1, data=0x00000000 1721179794.696077:pyrogue.memory.Transaction: Transaction done. type=1 id=21, address=0x0000000000020600, size=20 1721179794.696075:pyrogue.memory.Transaction: Created transaction type=1 id=22, address=0x0000000000000700, size=16 1721179794.696082:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Start transaction type = 1, Offset=0x800, lByte=0, hByte=255, tOff=0x0, tSize=256 1721179794.696083:pyrogue.memory.Master: Request transaction type=1 id=23 1721179794.696083:pyrogue.memory.Transaction: Created transaction type=1 id=23, address=0x0000000000000800, size=256 1721179794.696091:pyrogue.axi.AxiMemMap: Transaction id=22, addr 0x0000000000020700. Size=16, type=1, data=0x00000000 1721179794.696092:pyrogue.memory.Transaction: Transaction done. type=1 id=22, address=0x0000000000020700, size=16 1721179794.696101:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Start transaction type = 1, Offset=0x0, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696102:pyrogue.memory.Master: Request transaction type=1 id=24 1721179794.696103:pyrogue.memory.Transaction: Created transaction type=1 id=24, address=0x0000000000000000, size=4 1721179794.696117:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameCnt: Start transaction type = 1, Offset=0x4, lByte=0, hByte=7, tOff=0x0, tSize=8 1721179794.696118:pyrogue.memory.Master: Request transaction type=1 id=25 1721179794.696118:pyrogue.memory.Transaction: Created transaction type=1 id=25, address=0x0000000000000004, size=8 1721179794.696120:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRate: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696121:pyrogue.memory.Master: Request transaction type=1 id=26 1721179794.696121:pyrogue.memory.Transaction: Created transaction type=1 id=26, address=0x000000000000000c, size=4 1721179794.696123:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMax: Start transaction type = 1, Offset=0x10, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696124:pyrogue.memory.Master: Request transaction type=1 id=27 1721179794.696127:pyrogue.memory.Transaction: Created transaction type=1 id=27, address=0x0000000000000010, size=4 1721179794.696128:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMin: Start transaction type = 1, Offset=0x14, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696129:pyrogue.memory.Master: Request transaction type=1 id=28 1721179794.696130:pyrogue.memory.Transaction: Created transaction type=1 id=28, address=0x0000000000000014, size=4 1721179794.696132:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidth: Start transaction type = 1, Offset=0x18, lByte=0, hByte=7, tOff=0x0, tSize=8 1721179794.696133:pyrogue.memory.Master: Request transaction type=1 id=29 1721179794.696133:pyrogue.memory.Transaction: Created transaction type=1 id=29, address=0x0000000000000018, size=8 1721179794.696135:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMax: Start transaction type = 1, Offset=0x20, lByte=0, hByte=7, tOff=0x0, tSize=8 1721179794.696135:pyrogue.memory.Master: Request transaction type=1 id=30 1721179794.696136:pyrogue.memory.Transaction: Created transaction type=1 id=30, address=0x0000000000000020, size=8 1721179794.696145:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMin: Start transaction type = 1, Offset=0x28, lByte=0, hByte=7, tOff=0x0, tSize=8 1721179794.696146:pyrogue.memory.Master: Request transaction type=1 id=31 1721179794.696146:pyrogue.memory.Transaction: Created transaction type=1 id=31, address=0x0000000000000028, size=8 1721179794.696148:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSize: Start transaction type = 1, Offset=0x30, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696148:pyrogue.memory.Master: Request transaction type=1 id=32 1721179794.696149:pyrogue.memory.Transaction: Created transaction type=1 id=32, address=0x0000000000000030, size=4 1721179794.696156:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMax: Start transaction type = 1, Offset=0x34, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696156:pyrogue.memory.Master: Request transaction type=1 id=33 1721179794.696157:pyrogue.memory.Transaction: Created transaction type=1 id=33, address=0x0000000000000034, size=4 1721179794.696158:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMin: Start transaction type = 1, Offset=0x38, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696159:pyrogue.memory.Master: Request transaction type=1 id=34 1721179794.696159:pyrogue.memory.Transaction: Created transaction type=1 id=34, address=0x0000000000000038, size=4 1721179794.696163:pyrogue.axi.AxiMemMap: Transaction id=23, addr 0x0000000000020800. Size=256, type=1, data=0x00000000 1721179794.696164:pyrogue.memory.Transaction: Transaction done. type=1 id=23, address=0x0000000000020800, size=256 1721179794.696165:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Start transaction type = 1, Offset=0x0, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696166:pyrogue.memory.Master: Request transaction type=1 id=35 1721179794.696166:pyrogue.memory.Transaction: Created transaction type=1 id=35, address=0x0000000000000000, size=4 1721179794.696167:pyrogue.axi.AxiMemMap: Transaction id=24, addr 0x0000000000060000. Size=4, type=1, data=0x1082405649 1721179794.696167:pyrogue.memory.Transaction: Transaction done. type=1 id=24, address=0x0000000000060000, size=4 1721179794.696171:pyrogue.axi.AxiMemMap: Transaction id=25, addr 0x0000000000060004. Size=8, type=1, data=0x00000000 1721179794.696171:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameCnt: Start transaction type = 1, Offset=0x4, lByte=0, hByte=7, tOff=0x0, tSize=8 1721179794.696171:pyrogue.memory.Transaction: Transaction done. type=1 id=25, address=0x0000000000060004, size=8 1721179794.696172:pyrogue.memory.Master: Request transaction type=1 id=36 1721179794.696174:pyrogue.memory.Transaction: Created transaction type=1 id=36, address=0x0000000000000004, size=8 1721179794.696175:pyrogue.axi.AxiMemMap: Transaction id=26, addr 0x000000000006000c. Size=4, type=1, data=0x00000000 1721179794.696180:pyrogue.memory.Transaction: Transaction done. type=1 id=26, address=0x000000000006000c, size=4 1721179794.696177:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRate: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696185:pyrogue.memory.Master: Request transaction type=1 id=37 1721179794.696185:pyrogue.memory.Transaction: Created transaction type=1 id=37, address=0x000000000000000c, size=4 1721179794.696187:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMax: Start transaction type = 1, Offset=0x10, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696183:pyrogue.axi.AxiMemMap: Transaction id=27, addr 0x0000000000060010. Size=4, type=1, data=0x00000000 1721179794.696189:pyrogue.memory.Master: Request transaction type=1 id=38 1721179794.696189:pyrogue.memory.Transaction: Created transaction type=1 id=38, address=0x0000000000000010, size=4 1721179794.696189:pyrogue.memory.Transaction: Transaction done. type=1 id=27, address=0x0000000000060010, size=4 1721179794.696193:pyrogue.axi.AxiMemMap: Transaction id=28, addr 0x0000000000060014. Size=4, type=1, data=0x00000000 1721179794.696194:pyrogue.memory.Transaction: Transaction done. type=1 id=28, address=0x0000000000060014, size=4 1721179794.696197:pyrogue.axi.AxiMemMap: Transaction id=29, addr 0x0000000000060018. Size=8, type=1, data=0x00000000 1721179794.696197:pyrogue.memory.Transaction: Transaction done. type=1 id=29, address=0x0000000000060018, size=8 1721179794.696200:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMin: Start transaction type = 1, Offset=0x14, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696200:pyrogue.axi.AxiMemMap: Transaction id=30, addr 0x0000000000060020. Size=8, type=1, data=0x00000000 1721179794.696201:pyrogue.memory.Master: Request transaction type=1 id=39 1721179794.696202:pyrogue.memory.Transaction: Created transaction type=1 id=39, address=0x0000000000000014, size=4 1721179794.696201:pyrogue.memory.Transaction: Transaction done. type=1 id=30, address=0x0000000000060020, size=8 1721179794.696204:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidth: Start transaction type = 1, Offset=0x18, lByte=0, hByte=7, tOff=0x0, tSize=8 1721179794.696205:pyrogue.memory.Master: Request transaction type=1 id=40 1721179794.696205:pyrogue.memory.Transaction: Created transaction type=1 id=40, address=0x0000000000000018, size=8 1721179794.696206:pyrogue.axi.AxiMemMap: Transaction id=31, addr 0x0000000000060028. Size=8, type=1, data=0x00000000 1721179794.696207:pyrogue.memory.Transaction: Transaction done. type=1 id=31, address=0x0000000000060028, size=8 1721179794.696210:pyrogue.axi.AxiMemMap: Transaction id=32, addr 0x0000000000060030. Size=4, type=1, data=0x00000000 1721179794.696210:pyrogue.memory.Transaction: Transaction done. type=1 id=32, address=0x0000000000060030, size=4 1721179794.696207:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMax: Start transaction type = 1, Offset=0x20, lByte=0, hByte=7, tOff=0x0, tSize=8 1721179794.696212:pyrogue.memory.Master: Request transaction type=1 id=41 1721179794.696212:pyrogue.axi.AxiMemMap: Transaction id=33, addr 0x0000000000060034. Size=4, type=1, data=0x00000000 1721179794.696215:pyrogue.memory.Transaction: Transaction done. type=1 id=33, address=0x0000000000060034, size=4 1721179794.696213:pyrogue.memory.Transaction: Created transaction type=1 id=41, address=0x0000000000000020, size=8 1721179794.696221:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMin: Start transaction type = 1, Offset=0x28, lByte=0, hByte=7, tOff=0x0, tSize=8 1721179794.696221:pyrogue.memory.Master: Request transaction type=1 id=42 1721179794.696222:pyrogue.memory.Transaction: Created transaction type=1 id=42, address=0x0000000000000028, size=8 1721179794.696217:pyrogue.axi.AxiMemMap: Transaction id=34, addr 0x0000000000060038. Size=4, type=1, data=0x00000000 1721179794.696224:pyrogue.memory.Transaction: Transaction done. type=1 id=34, address=0x0000000000060038, size=4 1721179794.696230:pyrogue.axi.AxiMemMap: Transaction id=35, addr 0x0000000000068000. Size=4, type=1, data=0x1082405649 1721179794.696231:pyrogue.memory.Transaction: Transaction done. type=1 id=35, address=0x0000000000068000, size=4 1721179794.696234:pyrogue.axi.AxiMemMap: Transaction id=36, addr 0x0000000000068004. Size=8, type=1, data=0x00000000 1721179794.696235:pyrogue.memory.Transaction: Transaction done. type=1 id=36, address=0x0000000000068004, size=8 1721179794.696237:pyrogue.axi.AxiMemMap: Transaction id=37, addr 0x000000000006800c. Size=4, type=1, data=0x00000000 1721179794.696237:pyrogue.memory.Transaction: Transaction done. type=1 id=37, address=0x000000000006800c, size=4 1721179794.696225:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSize: Start transaction type = 1, Offset=0x30, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696241:pyrogue.memory.Master: Request transaction type=1 id=43 1721179794.696241:pyrogue.memory.Transaction: Created transaction type=1 id=43, address=0x0000000000000030, size=4 1721179794.696239:pyrogue.axi.AxiMemMap: Transaction id=38, addr 0x0000000000068010. Size=4, type=1, data=0x00000000 1721179794.696243:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMax: Start transaction type = 1, Offset=0x34, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696244:pyrogue.memory.Transaction: Transaction done. type=1 id=38, address=0x0000000000068010, size=4 1721179794.696245:pyrogue.memory.Master: Request transaction type=1 id=44 1721179794.696245:pyrogue.memory.Transaction: Created transaction type=1 id=44, address=0x0000000000000034, size=4 1721179794.696247:pyrogue.axi.AxiMemMap: Transaction id=39, addr 0x0000000000068014. Size=4, type=1, data=0x00000000 1721179794.696247:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMin: Start transaction type = 1, Offset=0x38, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696248:pyrogue.memory.Transaction: Transaction done. type=1 id=39, address=0x0000000000068014, size=4 1721179794.696249:pyrogue.memory.Master: Request transaction type=1 id=45 1721179794.696254:pyrogue.axi.AxiMemMap: Transaction id=40, addr 0x0000000000068018. Size=8, type=1, data=0x00000000 1721179794.696254:pyrogue.memory.Transaction: Created transaction type=1 id=45, address=0x0000000000000038, size=4 1721179794.696255:pyrogue.memory.Transaction: Transaction done. type=1 id=40, address=0x0000000000068018, size=8 1721179794.696258:pyrogue.axi.AxiMemMap: Transaction id=41, addr 0x0000000000068020. Size=8, type=1, data=0x00000000 1721179794.696259:pyrogue.memory.Transaction: Transaction done. type=1 id=41, address=0x0000000000068020, size=8 1721179794.696262:pyrogue.axi.AxiMemMap: Transaction id=42, addr 0x0000000000068028. Size=8, type=1, data=0x00000000 1721179794.696263:pyrogue.memory.Transaction: Transaction done. type=1 id=42, address=0x0000000000068028, size=8 1721179794.696265:pyrogue.axi.AxiMemMap: Transaction id=43, addr 0x0000000000068030. Size=4, type=1, data=0x00000000 1721179794.696265:pyrogue.memory.Transaction: Transaction done. type=1 id=43, address=0x0000000000068030, size=4 1721179794.696267:pyrogue.axi.AxiMemMap: Transaction id=44, addr 0x0000000000068034. Size=4, type=1, data=0x00000000 1721179794.696268:pyrogue.memory.Transaction: Transaction done. type=1 id=44, address=0x0000000000068034, size=4 1721179794.696268:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.VendorID: Start transaction type = 1, Offset=0x0, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696270:pyrogue.memory.Master: Request transaction type=1 id=46 1721179794.696270:pyrogue.memory.Transaction: Created transaction type=1 id=46, address=0x0000000000000000, size=4 1721179794.696270:pyrogue.axi.AxiMemMap: Transaction id=45, addr 0x0000000000068038. Size=4, type=1, data=0x00000000 1721179794.696271:pyrogue.memory.Transaction: Transaction done. type=1 id=45, address=0x0000000000068038, size=4 1721179794.696272:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.Command: Start transaction type = 1, Offset=0x4, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696277:pyrogue.memory.Master: Request transaction type=1 id=47 1721179794.696278:pyrogue.memory.Transaction: Created transaction type=1 id=47, address=0x0000000000000004, size=4 1721179794.696273:pyrogue.axi.AxiMemMap: Transaction id=46, addr 0x0000000000010000. Size=4, type=1, data=0x540023370 1721179794.696282:pyrogue.memory.Transaction: Transaction done. type=1 id=46, address=0x0000000000010000, size=4 1721179794.696283:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.RevisionID: Start transaction type = 1, Offset=0x8, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696284:pyrogue.memory.Master: Request transaction type=1 id=48 1721179794.696284:pyrogue.memory.Transaction: Created transaction type=1 id=48, address=0x0000000000000008, size=4 1721179794.696285:pyrogue.axi.AxiMemMap: Transaction id=47, addr 0x0000000000010004. Size=4, type=1, data=0x01048582 1721179794.696286:pyrogue.memory.Transaction: Transaction done. type=1 id=47, address=0x0000000000010004, size=4 1721179794.696286:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696287:pyrogue.memory.Master: Request transaction type=1 id=49 1721179794.696288:pyrogue.memory.Transaction: Created transaction type=1 id=49, address=0x000000000000000c, size=4 1721179794.696288:pyrogue.axi.AxiMemMap: Transaction id=48, addr 0x0000000000010008. Size=4, type=1, data=0x293601280 1721179794.696289:pyrogue.memory.Transaction: Transaction done. type=1 id=48, address=0x0000000000010008, size=4 1721179794.696289:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[0]: Start transaction type = 1, Offset=0x10, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696291:pyrogue.memory.Master: Request transaction type=1 id=50 1721179794.696292:pyrogue.memory.Transaction: Created transaction type=1 id=50, address=0x0000000000000010, size=4 1721179794.696292:pyrogue.axi.AxiMemMap: Transaction id=49, addr 0x000000000001000c. Size=4, type=1, data=0x00000016 1721179794.696293:pyrogue.memory.Transaction: Transaction done. type=1 id=49, address=0x000000000001000c, size=4 1721179794.696293:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[1]: Start transaction type = 1, Offset=0x14, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696294:pyrogue.memory.Master: Request transaction type=1 id=51 1721179794.696295:pyrogue.memory.Transaction: Created transaction type=1 id=51, address=0x0000000000000014, size=4 1721179794.696295:pyrogue.axi.AxiMemMap: Transaction id=50, addr 0x0000000000010010. Size=4, type=1, data=0x4076863488 1721179794.696296:pyrogue.memory.Transaction: Transaction done. type=1 id=50, address=0x0000000000010010, size=4 1721179794.696297:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[2]: Start transaction type = 1, Offset=0x18, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696298:pyrogue.memory.Master: Request transaction type=1 id=52 1721179794.696298:pyrogue.memory.Transaction: Created transaction type=1 id=52, address=0x0000000000000018, size=4 1721179794.696298:pyrogue.axi.AxiMemMap: Transaction id=51, addr 0x0000000000010014. Size=4, type=1, data=0x00000000 1721179794.696299:pyrogue.memory.Transaction: Transaction done. type=1 id=51, address=0x0000000000010014, size=4 1721179794.696300:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[3]: Start transaction type = 1, Offset=0x1c, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696301:pyrogue.memory.Master: Request transaction type=1 id=53 1721179794.696301:pyrogue.memory.Transaction: Created transaction type=1 id=53, address=0x000000000000001c, size=4 1721179794.696302:pyrogue.axi.AxiMemMap: Transaction id=52, addr 0x0000000000010018. Size=4, type=1, data=0x00000000 1721179794.696302:pyrogue.memory.Transaction: Transaction done. type=1 id=52, address=0x0000000000010018, size=4 1721179794.696305:pyrogue.axi.AxiMemMap: Transaction id=53, addr 0x000000000001001c. Size=4, type=1, data=0x00000000 1721179794.696309:pyrogue.memory.Transaction: Transaction done. type=1 id=53, address=0x000000000001001c, size=4 1721179794.696310:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[4]: Start transaction type = 1, Offset=0x20, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696311:pyrogue.memory.Master: Request transaction type=1 id=54 1721179794.696312:pyrogue.memory.Transaction: Created transaction type=1 id=54, address=0x0000000000000020, size=4 1721179794.696315:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[5]: Start transaction type = 1, Offset=0x24, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696315:pyrogue.memory.Master: Request transaction type=1 id=55 1721179794.696316:pyrogue.memory.Transaction: Created transaction type=1 id=55, address=0x0000000000000024, size=4 1721179794.696317:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CardbusCisPointer: Start transaction type = 1, Offset=0x28, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696326:pyrogue.memory.Master: Request transaction type=1 id=56 1721179794.696326:pyrogue.memory.Transaction: Created transaction type=1 id=56, address=0x0000000000000028, size=4 1721179794.696328:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.SubVendorId: Start transaction type = 1, Offset=0x2c, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696321:pyrogue.axi.AxiMemMap: Transaction id=54, addr 0x0000000000010020. Size=4, type=1, data=0x00000000 1721179794.696329:pyrogue.memory.Master: Request transaction type=1 id=57 1721179794.696330:pyrogue.memory.Transaction: Transaction done. type=1 id=54, address=0x0000000000010020, size=4 1721179794.696330:pyrogue.memory.Transaction: Created transaction type=1 id=57, address=0x000000000000002c, size=4 1721179794.696333:pyrogue.axi.AxiMemMap: Transaction id=55, addr 0x0000000000010024. Size=4, type=1, data=0x00000000 1721179794.696333:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.ExpansionRomBaseAddress: Start transaction type = 1, Offset=0x30, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696334:pyrogue.memory.Transaction: Transaction done. type=1 id=55, address=0x0000000000010024, size=4 1721179794.696335:pyrogue.memory.Master: Request transaction type=1 id=58 1721179794.696335:pyrogue.memory.Transaction: Created transaction type=1 id=58, address=0x0000000000000030, size=4 1721179794.696337:pyrogue.axi.AxiMemMap: Transaction id=56, addr 0x0000000000010028. Size=4, type=1, data=0x00000000 1721179794.696337:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CapabilitiesPointer: Start transaction type = 1, Offset=0x34, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696337:pyrogue.memory.Transaction: Transaction done. type=1 id=56, address=0x0000000000010028, size=4 1721179794.696339:pyrogue.memory.Master: Request transaction type=1 id=59 1721179794.696340:pyrogue.memory.Transaction: Created transaction type=1 id=59, address=0x0000000000000034, size=4 1721179794.696341:pyrogue.axi.AxiMemMap: Transaction id=57, addr 0x000000000001002c. Size=4, type=1, data=0x540023370 1721179794.696342:pyrogue.memory.Transaction: Transaction done. type=1 id=57, address=0x000000000001002c, size=4 1721179794.696342:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine: Start transaction type = 1, Offset=0x3c, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696343:pyrogue.memory.Master: Request transaction type=1 id=60 1721179794.696343:pyrogue.memory.Transaction: Created transaction type=1 id=60, address=0x000000000000003c, size=4 1721179794.696344:pyrogue.axi.AxiMemMap: Transaction id=58, addr 0x0000000000010030. Size=4, type=1, data=0x00000000 1721179794.696345:pyrogue.memory.Transaction: Transaction done. type=1 id=58, address=0x0000000000010030, size=4 1721179794.696345:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Start transaction type = 1, Offset=0x40, lByte=0, hByte=191, tOff=0x0, tSize=192 1721179794.696346:pyrogue.memory.Master: Request transaction type=1 id=61 1721179794.696346:pyrogue.memory.Transaction: Created transaction type=1 id=61, address=0x0000000000000040, size=192 1721179794.696347:pyrogue.axi.AxiMemMap: Transaction id=59, addr 0x0000000000010034. Size=4, type=1, data=0x00000064 1721179794.696360:pyrogue.memory.Transaction: Transaction done. type=1 id=59, address=0x0000000000010034, size=4 1721179794.696363:pyrogue.axi.AxiMemMap: Transaction id=60, addr 0x000000000001003c. Size=4, type=1, data=0x00000511 1721179794.696363:pyrogue.memory.Transaction: Transaction done. type=1 id=60, address=0x000000000001003c, size=4 1721179794.696380:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Rnw: Start transaction type = 1, Offset=0x0, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696381:pyrogue.memory.Master: Request transaction type=1 id=62 1721179794.696382:pyrogue.memory.Transaction: Created transaction type=1 id=62, address=0x0000000000000000, size=4 1721179794.696387:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Done: Start transaction type = 1, Offset=0x4, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696388:pyrogue.memory.Master: Request transaction type=1 id=63 1721179794.696388:pyrogue.memory.Transaction: Created transaction type=1 id=63, address=0x0000000000000004, size=4 1721179794.696390:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Addr: Start transaction type = 1, Offset=0x8, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696390:pyrogue.memory.Master: Request transaction type=1 id=64 1721179794.696391:pyrogue.memory.Transaction: Created transaction type=1 id=64, address=0x0000000000000008, size=4 1721179794.696392:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Data: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696393:pyrogue.memory.Master: Request transaction type=1 id=65 1721179794.696393:pyrogue.memory.Transaction: Created transaction type=1 id=65, address=0x000000000000000c, size=4 1721179794.696413:pyrogue.axi.AxiMemMap: Transaction id=61, addr 0x0000000000010040. Size=192, type=1, data=0x00000000 1721179794.696414:pyrogue.memory.Transaction: Transaction done. type=1 id=61, address=0x0000000000010040, size=192 1721179794.696416:pyrogue.axi.AxiMemMap: Transaction id=62, addr 0x0000000000070000. Size=4, type=1, data=0x00000000 1721179794.696417:pyrogue.memory.Transaction: Transaction done. type=1 id=62, address=0x0000000000070000, size=4 1721179794.696419:pyrogue.axi.AxiMemMap: Transaction id=63, addr 0x0000000000070004. Size=4, type=1, data=0x00000001 1721179794.696419:pyrogue.memory.Transaction: Transaction done. type=1 id=63, address=0x0000000000070004, size=4 1721179794.696422:pyrogue.axi.AxiMemMap: Transaction id=64, addr 0x0000000000070008. Size=4, type=1, data=0x00000000 1721179794.696422:pyrogue.memory.Transaction: Transaction done. type=1 id=64, address=0x0000000000070008, size=4 1721179794.696424:pyrogue.axi.AxiMemMap: Transaction id=65, addr 0x000000000007000c. Size=4, type=1, data=0x00000000 1721179794.696425:pyrogue.memory.Transaction: Transaction done. type=1 id=65, address=0x000000000007000c, size=4 1721179794.696430:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaVersion: Transaction complete 1721179794.696434:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.ScratchPad: Transaction complete 1721179794.696436:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UpTimeCnt: Transaction complete 1721179794.696446:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReloadHalt: Transaction complete 1721179794.696448:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReload: Transaction complete 1721179794.696449:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaReloadAddress: Transaction complete 1721179794.696451:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UserReset: Transaction complete 1721179794.696453:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FdSerial: Transaction complete 1721179794.696455:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_SIZE_G: Transaction complete 1721179794.696457:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.Reserved: Transaction complete 1721179794.696459:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DRIVER_TYPE_ID_G: Transaction complete 1721179794.696467:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.XIL_DEVICE_G: Transaction complete 1721179794.696469:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_CLK_FREQ_C: Transaction complete 1721179794.696472:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BOOT_PROM_G: Transaction complete 1721179794.696474:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DMA_AXIS_CONFIG_G_TDATA_BYTES_C: Transaction complete 1721179794.696489:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AXI_PCIE_CONFIG_C_ADDR_WIDTH_C: Transaction complete 1721179794.696493:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.AppClkFreq: Transaction complete 1721179794.696495:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.PCIE_HW_TYPE_G: Transaction complete 1721179794.696497:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceId: Transaction complete 1721179794.696499:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.GitHash: Transaction complete 1721179794.696501:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceDna: Transaction complete 1721179794.696503:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Transaction complete 1721179794.696522:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.CntRst: Transaction complete 1721179794.696548:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameCnt: Transaction complete 1721179794.696550:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRate: Transaction complete 1721179794.696552:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMax: Transaction complete 1721179794.696554:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameRateMin: Transaction complete 1721179794.696556:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidth: Transaction complete 1721179794.696559:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMax: Transaction complete 1721179794.696562:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].RawBandwidthMin: Transaction complete 1721179794.696566:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSize: Transaction complete 1721179794.696568:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMax: Transaction complete 1721179794.696570:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaIbAxisMon.Ch[0].FrameSizeMin: Transaction complete 1721179794.696578:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.CntRst: Transaction complete 1721179794.696589:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameCnt: Transaction complete 1721179794.696591:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRate: Transaction complete 1721179794.696593:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMax: Transaction complete 1721179794.696595:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameRateMin: Transaction complete 1721179794.696597:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidth: Transaction complete 1721179794.696600:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMax: Transaction complete 1721179794.696605:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].RawBandwidthMin: Transaction complete 1721179794.696614:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSize: Transaction complete 1721179794.696616:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMax: Transaction complete 1721179794.696618:pyrogue.memory.block.PcieTop.AxiPcieCore.DmaObAxisMon.Ch[0].FrameSizeMin: Transaction complete 1721179794.696628:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.VendorID: Transaction complete 1721179794.696630:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.Command: Transaction complete 1721179794.696633:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.RevisionID: Transaction complete 1721179794.696647:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CacheLineSize: Transaction complete 1721179794.696660:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[0]: Transaction complete 1721179794.696662:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[1]: Transaction complete 1721179794.696664:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[2]: Transaction complete 1721179794.696665:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[3]: Transaction complete 1721179794.696667:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[4]: Transaction complete 1721179794.696669:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.BaseAddressBar[5]: Transaction complete 1721179794.696671:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CardbusCisPointer: Transaction complete 1721179794.696673:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.SubVendorId: Transaction complete 1721179794.696675:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.ExpansionRomBaseAddress: Transaction complete 1721179794.696677:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.CapabilitiesPointer: Transaction complete 1721179794.696681:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.InterruptLine: Transaction complete 1721179794.696685:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiPciePhy.DevSpecRegion: Transaction complete 1721179794.696697:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.DataWrBus: Transaction complete 1721179794.696698:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.AddrBus: Transaction complete 1721179794.696699:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.DataRdBus: Transaction complete 1721179794.696699:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.TranSize: Transaction complete 1721179794.696699:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstTran: Transaction complete 1721179794.696700:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronMt28ew.BurstData: Transaction complete 1721179794.696703:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].PasswordLock: Transaction complete 1721179794.696703:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].ModeReg: Transaction complete 1721179794.696704:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Transaction complete 1721179794.696704:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179794.696709:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Transaction complete 1721179794.696712:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].PasswordLock: Transaction complete 1721179794.696712:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].ModeReg: Transaction complete 1721179794.696713:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].AddrReg: Transaction complete 1721179794.696713:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].CmdReg: Transaction complete 1721179794.696713:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[1].DataReg: Transaction complete 1721179794.696719:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Rnw: Transaction complete 1721179794.696721:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Done: Transaction complete 1721179794.696724:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Addr: Transaction complete 1721179794.696725:pyrogue.memory.block.PcieTop.AxiPcieCore.AxilBridge.Regs.Data: Transaction complete 1721179794.696747:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BOOT_PROM_G: Start transaction type = 1, Offset=0x414, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696747:pyrogue.memory.Master: Request transaction type=1 id=66 1721179794.696748:pyrogue.memory.Transaction: Created transaction type=1 id=66, address=0x0000000000000414, size=4 1721179794.696771:pyrogue.axi.AxiMemMap: Transaction id=66, addr 0x0000000000020414. Size=4, type=1, data=0x00000002 1721179794.696771:pyrogue.memory.Transaction: Transaction done. type=1 id=66, address=0x0000000000020414, size=4 1721179794.696882:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BOOT_PROM_G: Transaction complete 1721179794.696911:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.GitHash: Start transaction type = 1, Offset=0x600, lByte=0, hByte=19, tOff=0x0, tSize=20 1721179794.696912:pyrogue.memory.Master: Request transaction type=1 id=67 1721179794.696912:pyrogue.memory.Transaction: Created transaction type=1 id=67, address=0x0000000000000600, size=20 1721179794.696931:pyrogue.axi.AxiMemMap: Transaction id=67, addr 0x0000000000020600. Size=20, type=1, data=0x00000000 1721179794.696931:pyrogue.memory.Transaction: Transaction done. type=1 id=67, address=0x0000000000020600, size=20 1721179794.696946:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.GitHash: Transaction complete 1721179794.696960:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaVersion: Start transaction type = 1, Offset=0x0, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.696964:pyrogue.memory.Master: Request transaction type=1 id=68 1721179794.696965:pyrogue.memory.Transaction: Created transaction type=1 id=68, address=0x0000000000000000, size=4 1721179794.697134:pyrogue.axi.AxiMemMap: Transaction id=68, addr 0x0000000000020000. Size=4, type=1, data=0x33882112 1721179794.697134:pyrogue.memory.Transaction: Transaction done. type=1 id=68, address=0x0000000000020000, size=4 1721179794.697135:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.FpgaVersion: Transaction complete 1721179794.697148:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UpTimeCnt: Start transaction type = 1, Offset=0x8, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179794.697149:pyrogue.memory.Master: Request transaction type=1 id=69 1721179794.697149:pyrogue.memory.Transaction: Created transaction type=1 id=69, address=0x0000000000000008, size=4 1721179794.697198:pyrogue.axi.AxiMemMap: Transaction id=69, addr 0x0000000000020008. Size=4, type=1, data=0x00000181 1721179794.697198:pyrogue.memory.Transaction: Transaction done. type=1 id=69, address=0x0000000000020008, size=4 1721179794.697203:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.UpTimeCnt: Transaction complete 1721179794.697219:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceDna: Start transaction type = 1, Offset=0x700, lByte=0, hByte=15, tOff=0x0, tSize=16 1721179794.697220:pyrogue.memory.Master: Request transaction type=1 id=70 1721179794.697220:pyrogue.memory.Transaction: Created transaction type=1 id=70, address=0x0000000000000700, size=16 1721179794.697231:pyrogue.axi.AxiMemMap: Transaction id=70, addr 0x0000000000020700. Size=16, type=1, data=0x00000000 1721179794.697231:pyrogue.memory.Transaction: Transaction done. type=1 id=70, address=0x0000000000020700, size=16 1721179794.697233:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.DeviceDna: Transaction complete 1721179794.697242:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Start transaction type = 1, Offset=0x800, lByte=0, hByte=255, tOff=0x0, tSize=256 1721179794.697243:pyrogue.memory.Master: Request transaction type=1 id=71 1721179794.697243:pyrogue.memory.Transaction: Created transaction type=1 id=71, address=0x0000000000000800, size=256 1721179794.697330:pyrogue.axi.AxiMemMap: Transaction id=71, addr 0x0000000000020800. Size=256, type=1, data=0x00000000 1721179794.697330:pyrogue.memory.Transaction: Transaction done. type=1 id=71, address=0x0000000000020800, size=256 1721179794.697334:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Transaction complete 1721179794.697474:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiVersion.BuildStamp: Start transaction type = 1, Offset=0x800, lByte=0, hByte=255, tOff=0x0, tSize=256 1721179794.697475:pyrogue.memory.Master: Request transaction type=1 id=72 1721179794.697476:pyrogue.memory.Transaction: Created transaction type=1 id=72, address=0x0000000000000800, size=256 1721179794.697539:pyrogue.axi.AxiMemMap: Transaction id=72, addr 0x0000000000020800. Size=256, type=1, data=0x00000000 1721179794.697540:pyrogue.memory.Transaction: Transaction done. type=1 id=72, address=0x0000000000020800, size=256 1721179794.697545:pyrogue.memory.block.Pcie######################################### Current Firmware Loaded on the PCIe card: ######################################### Path = PcieTop.AxiPcieCore.AxiVersion FwVersion = 0x2050000 UpTime = 0:03:01 GitHash = dirty (uncommitted code) XilinxDnaId = 0x40020000015060482cf06445 FwTarget = XilinxVariumC1100DmaLoopback BuildEnv = Vivado v2023.1 BuildServer = rdsrv411 (Ubuntu 20.04.6 LTS) BuildDate = Thu 11 Jul 2024 12:41:11 PM PDT Builder = ruckman ######################################### 0 : ../firmware/targets/XilinxVariumC1100/XilinxVariumC1100DmaLoopback/images/XilinxVariumC1100DmaLoopback-0x02050000-20240711124111-ruckman-dirty 1 : Exit Enter image to program into the PCIe card's PROM: PcieTop.AxiPcieCore.AxiMicronN25Q[0].LoadMcsFile: ../firmware/targets/XilinxVariumC1100/XilinxVariumC1100DmaLoopback/images/XilinxVariumC1100DmaLoopback-0x02050000-20240711124111-ruckman-dirty.mcs Top.AxiPcieCore.AxiVersion.BuildStamp: Transaction complete 1721179797.964862:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.964870:pyrogue.memory.Master: Request transaction type=2 id=73 1721179797.964872:pyrogue.memory.Transaction: Created transaction type=2 id=73, address=0x000000000000000c, size=4 1721179797.964940:pyrogue.axi.AxiMemMap: Transaction id=73, addr 0x000000000004000c. Size=4, type=2, data=0x2154168320 1721179797.964943:pyrogue.memory.Transaction: Transaction done. type=2 id=73, address=0x000000000004000c, size=4 1721179797.964954:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.964958:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.964962:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.966025:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.966026:pyrogue.memory.Master: Request transaction type=2 id=74 1721179797.966027:pyrogue.memory.Transaction: Created transaction type=2 id=74, address=0x000000000000000c, size=4 1721179797.966084:pyrogue.axi.AxiMemMap: Transaction id=74, addr 0x000000000004000c. Size=4, type=2, data=0x2157510656 1721179797.966087:pyrogue.memory.Transaction: Transaction done. type=2 id=74, address=0x000000000004000c, size=4 1721179797.966096:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.966098:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.966099:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967157:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].ModeReg: Start transaction type = 2, Offset=0x4, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.967159:pyrogue.memory.Master: Request transaction type=2 id=75 1721179797.967159:pyrogue.memory.Transaction: Created transaction type=2 id=75, address=0x0000000000000004, size=4 1721179797.967216:pyrogue.axi.AxiMemMap: Transaction id=75, addr 0x0000000000040004. Size=4, type=2, data=0x00000001 1721179797.967219:pyrogue.memory.Transaction: Transaction done. type=2 id=75, address=0x0000000000040004, size=4 1721179797.967243:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].ModeReg: Transaction complete 1721179797.967245:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].ModeReg: Transaction complete 1721179797.967246:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].ModeReg: Transaction complete 1721179797.967251:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.967252:pyrogue.memory.Master: Request transaction type=2 id=76 1721179797.967252:pyrogue.memory.Transaction: Created transaction type=2 id=76, address=0x000000000000000c, size=4 1721179797.967263:pyrogue.axi.AxiMemMap: Transaction id=76, addr 0x000000000004000c. Size=4, type=2, data=0x07340033 1721179797.967264:pyrogue.memory.Transaction: Transaction done. type=2 id=76, address=0x000000000004000c, size=4 1721179797.967270:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967271:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967272:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967277:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.967279:pyrogue.memory.Master: Request transaction type=1 id=77 1721179797.967279:pyrogue.memory.Transaction: Created transaction type=1 id=77, address=0x000000000000000c, size=4 1721179797.967287:pyrogue.axi.AxiMemMap: Transaction id=77, addr 0x000000000004000c. Size=4, type=1, data=0x00000128 1721179797.967298:pyrogue.memory.Transaction: Transaction done. type=1 id=77, address=0x000000000004000c, size=4 1721179797.967304:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967305:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967312:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.967313:pyrogue.memory.Master: Request transaction type=2 id=78 1721179797.967313:pyrogue.memory.Transaction: Created transaction type=2 id=78, address=0x000000000000000c, size=4 1721179797.967321:pyrogue.axi.AxiMemMap: Transaction id=78, addr 0x000000000004000c. Size=4, type=2, data=0x2147876864 1721179797.967321:pyrogue.memory.Transaction: Transaction done. type=2 id=78, address=0x000000000004000c, size=4 1721179797.967326:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967328:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967329:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967331:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.967332:pyrogue.memory.Master: Request transaction type=2 id=79 1721179797.967333:pyrogue.memory.Transaction: Created transaction type=2 id=79, address=0x000000000000000c, size=4 1721179797.967339:pyrogue.axi.AxiMemMap: Transaction id=79, addr 0x000000000004000c. Size=4, type=2, data=0x2159476736 1721179797.967340:pyrogue.memory.Transaction: Transaction done. type=2 id=79, address=0x000000000004000c, size=4 1721179797.967344:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967346:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967347:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.967351:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Start transaction type = 2, Offset=0x8, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.967351:pyrogue.memory.Master: Request transaction type=2 id=80 1721179797.967352:pyrogue.memory.Transaction: Created transaction type=2 id=80, address=0x0000000000000008, size=4 1721179797.967359:pyrogue.axi.AxiMemMap: Transaction id=80, addr 0x0000000000040008. Size=4, type=2, data=0x4294836224 1721179797.967359:pyrogue.memory.Transaction: Transaction done. type=2 id=80, address=0x0000000000040008, size=4 1721179797.967364:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Transaction complete 1721179797.967365:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Transaction complete 1721179797.967366:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Transaction complete 1721179797.968423:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968425:pyrogue.memory.Master: Request transaction type=2 id=81 1721179797.968425:pyrogue.memory.Transaction: Created transaction type=2 id=81, address=0x000000000000000c, size=4 1721179797.968433:pyrogue.axi.AxiMemMap: Transaction id=81, addr 0x000000000004000c. Size=4, type=2, data=0x07340033 1721179797.968433:pyrogue.memory.Transaction: Transaction done. type=2 id=81, address=0x000000000004000c, size=4 1721179797.968439:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968440:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968441:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968443:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968444:pyrogue.memory.Master: Request transaction type=1 id=82 1721179797.968449:pyrogue.memory.Transaction: Created transaction type=1 id=82, address=0x000000000000000c, size=4 1721179797.968457:pyrogue.axi.AxiMemMap: Transaction id=82, addr 0x000000000004000c. Size=4, type=1, data=0x00000129 1721179797.968458:pyrogue.memory.Transaction: Transaction done. type=1 id=82, address=0x000000000004000c, size=4 1721179797.968463:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968464:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968467:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968469:pyrogue.memory.Master: Request transaction type=2 id=83 1721179797.968469:pyrogue.memory.Transaction: Created transaction type=2 id=83, address=0x000000000000000c, size=4 1721179797.968475:pyrogue.axi.AxiMemMap: Transaction id=83, addr 0x000000000004000c. Size=4, type=2, data=0x2147876864 1721179797.968475:pyrogue.memory.Transaction: Transaction done. type=2 id=83, address=0x000000000004000c, size=4 1721179797.968480:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968482:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968482:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968485:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968485:pyrogue.memory.Master: Request transaction type=2 id=84 1721179797.968485:pyrogue.memory.Transaction: Created transaction type=2 id=84, address=0x000000000000000c, size=4 1721179797.968491:pyrogue.axi.AxiMemMap: Transaction id=84, addr 0x000000000004000c. Size=4, type=2, data=0x2159083522 1721179797.968492:pyrogue.memory.Transaction: Transaction done. type=2 id=84, address=0x000000000004000c, size=4 1721179797.968497:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968498:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968499:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968502:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968503:pyrogue.memory.Master: Request transaction type=2 id=85 1721179797.968504:pyrogue.memory.Transaction: Created transaction type=2 id=85, address=0x000000000000000c, size=4 1721179797.968510:pyrogue.axi.AxiMemMap: Transaction id=85, addr 0x000000000004000c. Size=4, type=2, data=0x07340033 1721179797.968510:pyrogue.memory.Transaction: Transaction done. type=2 id=85, address=0x000000000004000c, size=4 1721179797.968515:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968516:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968517:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968519:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968520:pyrogue.memory.Master: Request transaction type=1 id=86 1721179797.968520:pyrogue.memory.Transaction: Created transaction type=1 id=86, address=0x000000000000000c, size=4 1721179797.968526:pyrogue.axi.AxiMemMap: Transaction id=86, addr 0x000000000004000c. Size=4, type=1, data=0x00000001 1721179797.968527:pyrogue.memory.Transaction: Transaction done. type=1 id=86, address=0x000000000004000c, size=4 1721179797.968531:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968533:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968535:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968539:pyrogue.memory.Master: Request transaction type=2 id=87 1721179797.968539:pyrogue.memory.Transaction: Created transaction type=2 id=87, address=0x000000000000000c, size=4 1721179797.968545:pyrogue.axi.AxiMemMap: Transaction id=87, addr 0x000000000004000c. Size=4, type=2, data=0x07340033 1721179797.968545:pyrogue.memory.Transaction: Transaction done. type=2 id=87, address=0x000000000004000c, size=4 1721179797.968549:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968551:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968552:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968564:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968565:pyrogue.memory.Master: Request transaction type=1 id=88 1721179797.968565:pyrogue.memory.Transaction: Created transaction type=1 id=88, address=0x000000000000000c, size=4 1721179797.968571:pyrogue.axi.AxiMemMap: Transaction id=88, addr 0x000000000004000c. Size=4, type=1, data=0x00000001 1721179797.968572:pyrogue.memory.Transaction: Transaction done. type=1 id=88, address=0x000000000004000c, size=4 1721179797.968577:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968578:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968589:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968591:pyrogue.memory.Master: Request transaction type=2 id=89 1721179797.968591:pyrogue.memory.Transaction: Created transaction type=2 id=89, address=0x000000000000000c, size=4 1721179797.968597:pyrogue.axi.AxiMemMap: Transaction id=89, addr 0x000000000004000c. Size=4, type=2, data=0x07340033 1721179797.968597:pyrogue.memory.Transaction: Transaction done. type=2 id=89, address=0x000000000004000c, size=4 1721179797.968602:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968603:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968604:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968606:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968607:pyrogue.memory.Master: Request transaction type=1 id=90 1721179797.968607:pyrogue.memory.Transaction: Created transaction type=1 id=90, address=0x000000000000000c, size=4 1721179797.968614:pyrogue.axi.AxiMemMap: Transaction id=90, addr 0x000000000004000c. Size=4, type=1, data=0x00000001 1721179797.968614:pyrogue.memory.Transaction: Transaction done. type=1 id=90, address=0x000000000004000c, size=4 1721179797.968619:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968621:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968623:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968624:pyrogue.memory.Master: Request transaction type=2 id=91 1721179797.968625:pyrogue.memory.Transaction: Created transaction type=2 id=91, address=0x000000000000000c, size=4 1721179797.968631:pyrogue.axi.AxiMemMap: Transaction id=91, addr 0x000000000004000c. Size=4, type=2, data=0x07340033 1721179797.968632:pyrogue.memory.Transaction: Transaction done. type=2 id=91, address=0x000000000004000c, size=4 1721179797.968636:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968638:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968642:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968644:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968644:pyrogue.memory.Master: Request transaction type=1 id=92 1721179797.968645:pyrogue.memory.Transaction: Created transaction type=1 id=92, address=0x000000000000000c, size=4 1721179797.968651:pyrogue.axi.AxiMemMap: Transaction id=92, addr 0x000000000004000c. Size=4, type=1, data=0x00000001 1721179797.968652:pyrogue.memory.Transaction: Transaction done. type=1 id=92, address=0x000000000004000c, size=4 1721179797.968656:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968658:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968660:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968662:pyrogue.memory.Master: Request transaction type=2 id=93 1721179797.968662:pyrogue.memory.Transaction: Created transaction type=2 id=93, address=0x000000000000000c, size=4 1721179797.968668:pyrogue.axi.AxiMemMap: Transaction id=93, addr 0x000000000004000c. Size=4, type=2, data=0x07340033 1721179797.968668:pyrogue.memory.Transaction: Transaction done. type=2 id=93, address=0x000000000004000c, size=4 1721179797.968673:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968674:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968675:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968677:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968678:pyrogue.memory.Master: Request transaction type=1 id=94 1721179797.968678:pyrogue.memory.Transaction: Created transaction type=1 id=94, address=0x000000000000000c, size=4 1721179797.968684:pyrogue.axi.AxiMemMap: Transaction id=94, addr 0x000000000004000c. Size=4, type=1, data=0x00000129 1721179797.968685:pyrogue.memory.Transaction: Transaction done. type=1 id=94, address=0x000000000004000c, size=4 1721179797.968690:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968691:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968694:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968695:pyrogue.memory.Master: Request transaction type=2 id=95 1721179797.968695:pyrogue.memory.Transaction: Created transaction type=2 id=95, address=0x000000000000000c, size=4 1721179797.968701:pyrogue.axi.AxiMemMap: Transaction id=95, addr 0x000000000004000c. Size=4, type=2, data=0x2147876864 1721179797.968701:pyrogue.memory.Transaction: Transaction done. type=2 id=95, address=0x000000000004000c, size=4 1721179797.968706:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968707:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968708:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968711:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968711:pyrogue.memory.Master: Request transaction type=2 id=96 1721179797.968711:pyrogue.memory.Transaction: Created transaction type=2 id=96, address=0x000000000000000c, size=4 1721179797.968718:pyrogue.axi.AxiMemMap: Transaction id=96, addr 0x000000000004000c. Size=4, type=2, data=0x2155937794 1721179797.968718:pyrogue.memory.Transaction: Transaction done. type=2 id=96, address=0x000000000004000c, size=4 1721179797.968734:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968735:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968736:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968741:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968742:pyrogue.memory.Master: Request transaction type=2 id=97 1721179797.968743:pyrogue.memory.Transaction: Created transaction type=2 id=97, address=0x000000000000000c, size=4 1721179797.968750:pyrogue.axi.AxiMemMap: Transaction id=97, addr 0x000000000004000c. Size=4, type=2, data=0x10420225 1721179797.968751:pyrogue.memory.Transaction: Transaction done. type=2 id=97, address=0x000000000004000c, size=4 1721179797.968756:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968757:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968758:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968760:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968761:pyrogue.memory.Master: Request transaction type=1 id=98 1721179797.968761:pyrogue.memory.Transaction: Created transaction type=1 id=98, address=0x000000000000000c, size=4 1721179797.968768:pyrogue.axi.AxiMemMap: Transaction id=98, addr 0x000000000004000c. Size=4, type=1, data=0x00000032 1721179797.968769:pyrogue.memory.Transaction: Transaction done. type=1 id=98, address=0x000000000004000c, size=4 1721179797.968774:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968775:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968782:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968795:pyrogue.memory.Master: Request transaction type=2 id=99 1721179797.968795:pyrogue.memory.Transaction: Created transaction type=2 id=99, address=0x000000000000000c, size=4 1721179797.968803:pyrogue.axi.AxiMemMap: Transaction id=99, addr 0x000000000004000c. Size=4, type=2, data=0x10420226 1721179797.968804:pyrogue.memory.Transaction: Transaction done. type=2 id=99, address=0x000000000004000c, size=4 1721179797.968808:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968810:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968811:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968813:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968814:pyrogue.memory.Master: Request transaction type=1 id=100 1721179797.968814:pyrogue.memory.Transaction: Created transaction type=1 id=100, address=0x000000000000000c, size=4 1721179797.968833:pyrogue.axi.AxiMemMap: Transaction id=100, addr 0x000000000004000c. Size=4, type=1, data=0x00000187 1721179797.968834:pyrogue.memory.Transaction: Transaction done. type=1 id=100, address=0x000000000004000c, size=4 1721179797.968840:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968841:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968848:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968850:pyrogue.memory.Master: Request transaction type=2 id=101 1721179797.968850:pyrogue.memory.Transaction: Created transaction type=2 id=101, address=0x000000000000000c, size=4 1721179797.968858:pyrogue.axi.AxiMemMap: Transaction id=101, addr 0x000000000004000c. Size=4, type=2, data=0x10420227 1721179797.968862:pyrogue.memory.Transaction: Transaction done. type=2 id=101, address=0x000000000004000c, size=4 1721179797.968867:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968868:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968869:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968871:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968872:pyrogue.memory.Master: Request transaction type=1 id=102 1721179797.968872:pyrogue.memory.Transaction: Created transaction type=1 id=102, address=0x000000000000000c, size=4 1721179797.968880:pyrogue.axi.AxiMemMap: Transaction id=102, addr 0x000000000004000c. Size=4, type=1, data=0x00000033 1721179797.968881:pyrogue.memory.Transaction: Transaction done. type=1 id=102, address=0x000000000004000c, size=4 1721179797.968885:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968887:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968891:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968893:pyrogue.memory.Master: Request transaction type=2 id=103 1721179797.968893:pyrogue.memory.Transaction: Created transaction type=2 id=103, address=0x000000000000000c, size=4 1721179797.968900:pyrogue.axi.AxiMemMap: Transaction id=103, addr 0x000000000004000c. Size=4, type=2, data=0x00327681 1721179797.968901:pyrogue.memory.Transaction: Transaction done. type=2 id=103, address=0x000000000004000c, size=4 1721179797.968907:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968909:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968910:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968912:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968912:pyrogue.memory.Master: Request transaction type=1 id=104 1721179797.968913:pyrogue.memory.Transaction: Created transaction type=1 id=104, address=0x000000000000000c, size=4 1721179797.968920:pyrogue.axi.AxiMemMap: Transaction id=104, addr 0x000000000004000c. Size=4, type=1, data=0x00000002 1721179797.968921:pyrogue.memory.Transaction: Transaction done. type=1 id=104, address=0x000000000004000c, size=4 1721179797.968927:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968928:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968940:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968942:pyrogue.memory.Master: Request transaction type=2 id=105 1721179797.968942:pyrogue.memory.Transaction: Created transaction type=2 id=105, address=0x000000000000000c, size=4 1721179797.968949:pyrogue.axi.AxiMemMap: Transaction id=105, addr 0x000000000004000c. Size=4, type=2, data=0x08716289 1721179797.968949:pyrogue.memory.Transaction: Transaction done. type=2 id=105, address=0x000000000004000c, size=4 1721179797.968963:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968964:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968965:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968967:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179797.968968:pyrogue.memory.Master: Request transaPROM Manufacturer ID Code = 0x20 PROM Manufacturer Type = 0xbb PROM Manufacturer Capacity = 0x21 PROM Status Register = 0x2 PROM Volatile Config Reg = 0xfb Reading .MCS: Verifying PROM: ction type=1 id=106 1721179797.968976:pyrogue.memory.Transaction: Created transaction type=1 id=106, address=0x000000000000000c, size=4 1721179797.968984:pyrogue.axi.AxiMemMap: Transaction id=106, addr 0x000000000004000c. Size=4, type=1, data=0x00000251 1721179797.968985:pyrogue.memory.Transaction: Transaction done. type=1 id=106, address=0x000000000004000c, size=4 1721179797.968990:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179797.968992:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179808.729726:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179808.729737:pyrogue.memory.Master: Request transaction type=2 id=107 1721179808.729738:pyrogue.memory.Transaction: Created transaction type=2 id=107, address=0x000000000000000c, size=4 1721179808.729785:pyrogue.axi.AxiMemMap: Transaction id=107, addr 0x000000000004000c. Size=4, type=2, data=0x07340033 1721179808.729787:pyrogue.memory.Transaction: Transaction done. type=2 id=107, address=0x000000000004000c, size=4 1721179808.729793:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179808.729796:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179808.729798:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179808.729803:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 1, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179808.729804:pyrogue.memory.Master: Request transaction type=1 id=108 1721179808.729804:pyrogue.memory.Transaction: Created transaction type=1 id=108, address=0x000000000000000c, size=4 1721179808.729814:pyrogue.axi.AxiMemMap: Transaction id=108, addr 0x000000000004000c. Size=4, type=1, data=0x00000129 1721179808.729815:pyrogue.memory.Transaction: Transaction done. type=1 id=108, address=0x000000000004000c, size=4 1721179808.729819:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179808.729820:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179808.729904:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Start transaction type = 2, Offset=0x8, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179808.729905:pyrogue.memory.Master: Request transaction type=2 id=109 1721179808.729906:pyrogue.memory.Transaction: Created transaction type=2 id=109, address=0x0000000000000008, size=4 1721179808.729932:pyrogue.axi.AxiMemMap: Transaction id=109, addr 0x0000000000040008. Size=4, type=2, data=0x16785408 1721179808.729934:pyrogue.memory.Transaction: Transaction done. type=2 id=109, address=0x0000000000040008, size=4 1721179808.729939:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Transaction complete 1721179808.729941:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Transaction complete 1721179808.729942:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].AddrReg: Transaction complete 1721179808.729946:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Start transaction type = 2, Offset=0xc, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179808.729947:pyrogue.memory.Master: Request transaction type=2 id=110 1721179808.729947:pyrogue.memory.Transaction: Created transaction type=2 id=110, address=0x000000000000000c, size=4 1721179808.729956:pyrogue.axi.AxiMemMap: Transaction id=110, addr 0x000000000004000c. Size=4, type=2, data=0x01245444 1721179808.729957:pyrogue.memory.Transaction: Transaction done. type=2 id=110, address=0x000000000004000c, size=4 1721179808.729961:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179808.729962:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179808.729963:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].CmdReg: Transaction complete 1721179808.729969:pyrogue.m Addr = 0x1002004: MCS = 0xff != PROM = 0x0 ERROR:pyrogue.Command.BaseCommand.PcieTop.AxiPcieCore.AxiMicronN25Q[0].LoadMcsFile:verifyProm() Failed Traceback (most recent call last): File "/afs/slac.stanford.edu/g/reseng/vol31/anaconda/anaconda3/envs/rogue_v6.3.0/lib/python3.9/site-packages/pyrogue/_Command.py", line 119, in _doFunc ret = self._functionWrap(function=self._function, root=self.root, dev=self.parent, cmd=self, arg=arg) File "", line 1, in File "/afs/slac.stanford.edu/u/re/ruckman/projects/pgp-pcie-apps/firmware/submodules/axi-pcie-core/scripts/../../surf/python/surf/devices/micron/_AxiMicronN25Q.py", line 201, in _LoadMcsFile self.verifyProm() File "/afs/slac.stanford.edu/u/re/ruckman/projects/pgp-pcie-apps/firmware/submodules/axi-pcie-core/scripts/../../surf/python/surf/devices/micron/_AxiMicronN25Q.py", line 329, in verifyProm raise surf.misc.McsException('verifyProm() Failed\n\n') surf.misc._McsReader.McsException: verifyProm() Failed emory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Start transaction type = 1, Offset=0x200, lByte=0, hByte=3, tOff=0x0, tSize=4 1721179808.729972:pyrogue.memory.Master: Request transaction type=1 id=111 1721179808.729973:pyrogue.memory.Transaction: Created transaction type=1 id=111, address=0x0000000000000200, size=4 1721179808.730029:pyrogue.axi.AxiMemMap: Transaction id=111, addr 0x0000000000040200. Size=4, type=1, data=0x4294967295 1721179808.730030:pyrogue.memory.Transaction: Transaction done. type=1 id=111, address=0x0000000000040200, size=4 1721179808.730035:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Transaction complete 1721179808.730036:pyrogue.memory.block.PcieTop.AxiPcieCore.AxiMicronN25Q[0].DataReg: Transaction complete