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Type:
Bug
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Resolution: Unresolved
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Priority:
Trivial
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Component/s: None
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None
Related to terminating using these constants:
constant AXI_LITE_READ_SLAVE_EMPTY_OK_C : AxiLiteReadSlaveType := axiLiteReadSlaveEmptyInit(rresp => AXI_RESP_OK_C); constant AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C : AxiLiteReadSlaveType := axiLiteReadSlaveEmptyInit(rresp => AXI_RESP_SLVERR_C); constant AXI_LITE_READ_SLAVE_EMPTY_DECERR_C : AxiLiteReadSlaveType := axiLiteReadSlaveEmptyInit(rresp => AXI_RESP_DECERR_C); constant AXI_LITE_WRITE_SLAVE_EMPTY_OK_C : AxiLiteWriteSlaveType := axiLiteWriteSlaveEmptyInit(bresp => AXI_RESP_OK_C); constant AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C : AxiLiteWriteSlaveType := axiLiteWriteSlaveEmptyInit(bresp => AXI_RESP_SLVERR_C); constant AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C : AxiLiteWriteSlaveType := axiLiteWriteSlaveEmptyInit(bresp => AXI_RESP_DECERR_C);
Here's the Xilinx IP core's AXI-Lite protocol checker's message output:
1030000 : SurfAxiLiteProtocolCheckerTb.\\GEN_VEC(1)\ .U_Checker.inst.REP : BIT( 79) : WARNING : AXI_AUXM_RCAM_UNDERFLOW. Read CAM underflow.
1040000 : SurfAxiLiteProtocolCheckerTb.\\GEN_VEC(1)\ .U_Checker.inst.REP : BIT( 58) : ERROR : Invalid state x
1040000 : SurfAxiLiteProtocolCheckerTb.\\GEN_VEC(1)\ .U_Checker.inst.REP : BIT( 59) : WARNING : AXI_ERRS_RID: A slave can only give read data with an ID to match an outstanding read transaction. Spec: section A5.3.1.
1050000 : SurfAxiLiteProtocolCheckerTb.\\GEN_VEC(1)\ .U_Checker.inst.REP : BIT( 32) : WARNING : AXI_ERRS_BRESP_AW: A slave must not give a write response before the write address. Spec: section A3.3.1 and figure A3-7.