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Documentation
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Resolution: Unresolved
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Trivial
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None
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None
- Increase FIFO count widths from slv(ADDR_WIDTH_G-1 downto 0) to slv(ADDR_WIDTH_G downto 0)
- Resolve issue with XPM having (2^ADDR_WIDTH_G) + 2 effective entires when in FWFT mode
- Enable inferred to support (2^ADDR_WIDTH_G) fill, instead of (2^ADDR_WIDTH_G)-1
- Add LUTRAM without register support to ram/inferred/SimpleDualPortRam.vhd
- Remove the legacy (unused) XIL_DEVICE_G
- axi\axi-lite\rtl\AxiVersion.vhd
- axi\axi-lite\rtl\AxiVersionLegacy.vhd
- devices\Ti\ads42lb69\rtl\AxiAds42lb69Core.vhd
- protocols\clink\rtl\ClinkTop.vhd
- xilinx\general\rtl\ClkOutBufDiff.vhd
- xilinx\general\rtl\ClkOutBufSingle.vhd
- xilinx\general\rtl\DeviceDna.vhd
- xilinx\general\rtl\Iprog.vhd
- Rename all modules with duplicated names:
- .xilinx/7Series/general/rtl/InputBufferReg.vhd
- xilinx/UltraScale/general/rtl/InputBufferReg.vhd
- For AxiStreamMux.vhd:
- Change MODE_G" generic to "TDEST_MODE_G"
- Remove TDEST_LOW_G
- For AxiStreamDeMux.vhd:
- Change MODE_G" generic to "TDEST_MODE_G"
- Remove TDEST_LOW_G
- Remove TDEST_HIGH_G
- Fix the prefix names of AXI-Lite modules from "Axi" to "AxiLite"
- Fix the prefix names of AXI-Lite modules from "Axil" to "AxiLite"
- Remove AxiVersionLegacy (.py/.vhd)
- Remove existing AxiStreamFifo.vhd and renamed current "AxiStreamFifoV2.vhd" to "AxiStreamFifo.vhd"
- Everyone should be migrated to AxiStreamFifoV2.vhd
- And we think there are a few bugs in AxiStreamFifo.vhd that we never got around to resolve
- Appears that ARM is moving master/slave to Requester/Completer for the AMBA specs.
